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1. 发明授权

US07924069B2 Multi-modulus divider retiming circuit 有权
标题翻译：多模分频重新定时电路
公开(公告)号：US07924069B2
公开(公告)日：2011-04-12
申请号：US11560678
申请日：2006-11-16
申请人： Chiewcharn Narathong , Wenjun Su
发明人： Chiewcharn Narathong , Wenjun Su
IPC分类号： H03B19/00
CPC分类号： H03K23/667 , H03K21/10 , H03L7/1976
摘要： A multi-modulus divider (MMD) receives an MMD input signal and outputs an MMD output signal SOUT. The MMD includes a chain of modulus divider stages (MDSs). Each MDS receives an input signal, divides it by either two or three, and outputs the result as an output signal. Each MDS responds to its own modulus control signal that controls whether it divides by two or three. In one example, a sequential logic element outputs SOUT. The low jitter modulus control signal of one of the first MDS stages of the chain is used to place a sequential logic element into a first state. The output signal of one of the MDS stages in the middle of the chain is used to place the sequential logic element into a second state. Power consumption is low because the sequential logic element is not clocked at the high frequency of the MMD input signal.
摘要翻译：多模式分频器（MMD）接收MMD输入信号并输出MMD输出信号SOUT。 MMD包括模数分频器级链（MDS）。每个MDS接收一个输入信号，将其分为两个或三个，并输出结果作为输出信号。每个MDS响应自己的模数控制信号，控制它是否被二或三除。在一个示例中，顺序逻辑元件输出SOUT。链的第一MDS级之一的低抖动模数控制信号用于将顺序逻辑元件置于第一状态。链中间的MDS级之一的输出信号用于将顺序逻辑元件置于第二状态。功耗很低，因为顺序逻辑元件不在MMD输入信号的高频时钟。

2. 发明申请

US20090315621A1 AMPLIFIER WITH GAIN EXPANSION STAGE 有权
标题翻译：具增益放大器的放大器
公开(公告)号：US20090315621A1
公开(公告)日：2009-12-24
申请号：US12143669
申请日：2008-06-20
申请人： Chiewcharn Narathong , Sankaran Aniruddhan , Wenjun Su
发明人： Chiewcharn Narathong , Sankaran Aniruddhan , Wenjun Su
IPC分类号： H03F1/14 , H03F3/68
CPC分类号： H03F1/3276 , H03F1/301 , H03F1/308 , H03F1/3241 , H03F3/245 , H03F3/3022 , H03F2200/336 , H03F2200/451 , H03F2200/453 , H03F2203/30099 , H03F2203/30132 , H03F2203/7231
摘要： Techniques are disclosed for extending an amplifier's linear operating range by concatenating an amplifier exhibiting gain compression with a gain expansion stage. In an exemplary embodiment, a gain expansion stage incorporates a Class-B stage, a Class-AB stage, or a combination of the two. In an exemplary embodiment, both the gain compression stage and gain expansion stage are provided with a replica current biasing scheme to ensure stable biasing current over variations in temperature, process, and/or supply voltage. Further disclosed is an output voltage biasing scheme to set the DC output voltage to ensure maximum linear operating range.
摘要翻译：公开了通过将展现增益压缩的放大器与增益扩展级相连接来扩展放大器的线性工作范围的技术。在示例性实施例中，增益扩展阶段包括B类阶段，AB类阶段或两者的组合。在示例性实施例中，增益压缩级和增益扩展级均被提供有复制电流偏置方案，以确保温度，过程和/或电源电压变化的稳定的偏置电流。进一步公开了一种用于设置直流输出电压以确保最大线性工作范围的输出电压偏置方案。

3. 发明申请

US20080042699A1 LOW-POWER MODULUS DIVIDER STAGE 有权
标题翻译：低功率模块分频器级
公开(公告)号：US20080042699A1
公开(公告)日：2008-02-21
申请号：US11560973
申请日：2006-11-17
申请人： Chiewcharn Narathong , Wenjun Su
发明人： Chiewcharn Narathong , Wenjun Su
IPC分类号： H03B19/00
CPC分类号： H03K23/54
摘要： A modulus divider stage (MDS) includes first and second stages. The MDS receives a modulus divisor control signal S that determines whether the MDS stage operates in a divide-by-two mode or a divide-by-three mode. The MDS stage also receives a feedback modulus control signal from another MDS. When in the divide-by-two mode, the MDS divides by two regardless of the feedback modulus control signal. To conserve power, the first stage is unpowered when the MDS stage operates in the divide-by-two mode. When in the divide-by-three mode, the MDS stage either divides by two or by three depending on the feedback modulus control signal. To further reduce power consumption, the first stage is unpowered when the MDS stage is in the divide-by-three mode but is nonetheless performing a divide-by-two operation. A power-down transistor holds the output of the first stage at the proper logic level when the first stage is unpowered.
摘要翻译：模数分频器级（MDS）包括第一级和第二级。 MDS接收模数除数控制信号S，其确定MDS级是以二分模式还是三分模式操作。 MDS级还接收来自另一MDS的反馈模数控制信号。在二分模式下，无论反馈模数控制信号如何，MDS除以二。为了节省功率，当MDS阶段以二分模式运行时，第一级无功。在三分频模式下，根据反馈模数控制信号，MDS级分为2或3。为了进一步降低功耗，当MDS级处于三分频模式时，第一级没有动力，但仍然执行一个二分之一的操作。当第一级无功时，掉电晶体管将第一级的输出保持在适当的逻辑电平。

4. 发明申请

US20160254793A1 CLOCK AND DATA DRIVERS WITH ENHANCED TRANSCONDUCTANCE AND SUPPRESSED OUTPUT COMMON-MODE 审中-公开
标题翻译：具有增强的交叉和抑制输出通用模式的时钟和数据驱动器
公开(公告)号：US20160254793A1
公开(公告)日：2016-09-01
申请号：US15029777
申请日：2014-11-05
申请人： Wenjun SU , Guangming YIN , Quanqing ZHU , QUALCOMM INCORPORATED
发明人： Wenjun SU , Guangming YIN , Quanqing ZHU
IPC分类号： H03F3/45 , H03K5/12
CPC分类号： H03F3/45762 , H03F1/0277 , H03F3/211 , H03F3/45183 , H03F3/45609 , H03F3/72 , H03F2200/555 , H03F2200/72 , H03F2203/45288 , H03F2203/45301 , H03F2203/45511 , H03F2203/45638 , H03F2203/45644 , H03F2203/45702 , H03K5/12
摘要： Methods, apparatus, and means for maintaining a low output common-mode voltage in a driver are provided. One example apparatus includes a first differential amplifier stage configured to provide a differential output for the apparatus; and a second differential amplifier stage configured to drive the first differential amplifier stage, the second differential amplifier stage including a pair of pre-driver amplifiers, a pair of n-stage circuits, and an input skew averaging circuit, wherein each of the pair of n-stage units is split into two half blocks. The input skew averaging circuit is configured to suppress the output common-mode voltage by driving the blocks with complementary digital inputs to average out a skew in a gate-to-source voltage of the pair of n-stage circuits. For certain aspects, two feed-forward capacitors may be added to enhance the transconductance and operating speed of main transistors of the first differential amplifier stage.
摘要翻译：提供了用于在驱动器中维持低输出共模电压的方法，装置和装置。一个示例性设备包括：第一差分放大器级，被配置为提供用于该设备的差分输出; 以及第二差分放大器级，被配置为驱动所述第一差分放大器级，所述第二差分放大器级包括一对预驱动器放大器，一对n级电路和输入偏差平均电路，其中， n级单元分为两个半块。输入偏斜平均电路被配置为通过用互补数字输入驱动块来抑制输出共模电压，以平均一对n级电路的栅极至源极电压的偏移。对于某些方面，可以添加两个前馈电容器以增强第一差分放大器级的主晶体管的跨导和工作速度。

5. 发明授权

US08779859B2 Multi-cascode amplifier bias techniques 有权
标题翻译：多共源共栅放大器偏置技术
公开(公告)号：US08779859B2
公开(公告)日：2014-07-15
申请号：US13570062
申请日：2012-08-08
申请人： Wenjun Su , Chiewcharn Narathong , Guangming Yin , Aristotele Hadjichristos
发明人： Wenjun Su , Chiewcharn Narathong , Guangming Yin , Aristotele Hadjichristos
IPC分类号： H03F1/22
CPC分类号： H03F1/223 , H03F3/193
摘要： Techniques for generating bias voltages for a multi-cascode amplifier. In an aspect, a multi-cascode bias network is provided, each transistor in the bias network being a replica of a corresponding transistor in the multi-cascode amplifier, enabling accurate biasing of the transistors in the multi-cascode amplifier. In another aspect, a voltage supply for the multi-cascode amplifier is provided separately from a voltage supply for the replica bias network, to advantageously decouple variations in the amplifier voltage supply from the bias network voltage supply. In yet another aspect, the bias voltages of transistors in the multi-cascode amplifier may be configured by adjusting the impedance of resistive voltage dividers coupled to the transistor gate biases. As the gain of the amplifier depends on the bias voltages of the cascode amplifiers, the gain of the amplifier may be adjusted in this manner without introducing a variable gain element directly in the amplifier signal path.
摘要翻译：用于产生多共源共栅放大器偏置电压的技术。在一方面，提供了一种多共源共栅偏压网络，偏置网络中的每个晶体管是多共源共栅放大器中对应的晶体管的复制品，使多级共源共栅放大器中的晶体管能够精确偏置。在另一方面，用于多重共源共栅放大器的电压源与用于复制偏压网络的电压源分开提供，以有利地将放大器电压源与偏置网络电压源的变化分离。在另一方面，多并联放大器中的晶体管的偏置电压可以通过调整耦合到晶体管栅极偏置的电阻分压器的阻抗来配置。由于放大器的增益取决于共源共栅放大器的偏置电压，所以可以以这种方式调节放大器的增益，而不将可变增益元件直接引入放大器信号路径。

6. 发明授权

US08688058B2 Techniques for improving transmitter performance 失效
标题翻译：改善发射机性能的技术
公开(公告)号：US08688058B2
公开(公告)日：2014-04-01
申请号：US12277022
申请日：2008-11-24
申请人： Chiewcharn Narathong , Wenjun Su
发明人： Chiewcharn Narathong , Wenjun Su
IPC分类号： H04B1/04
CPC分类号： H03G3/3042 , H03F1/56
摘要： Exemplary embodiment are directed to preserving transmitter linearity in RF transceivers while reducing RX band noise for use with low-power voltage supplies. In one aspect, a programmable attenuation element may be provided on-chip at the output of a driver amplifier, prior to a matching network. In another aspect, the programmable attenuation element may include a plurality of switchable capacitors.
摘要翻译：示例性实施例涉及在RF收发器中保持发射机线性度，同时降低用于低功率电源的RX频带噪声。在一个方面，可以在匹配网络之前在驱动器放大器的输出处片上设置可编程衰减元件。在另一方面，可编程衰减元件可以包括多个可切换电容器。

7. 发明授权

US07719313B2 Versatile and compact DC-coupled CML buffer 有权
标题翻译：通用紧凑的直流耦合CML缓冲器
公开(公告)号：US07719313B2
公开(公告)日：2010-05-18
申请号：US11560737
申请日：2006-11-16
申请人： Chiewcharn Narathong , Wenjun Su
发明人： Chiewcharn Narathong , Wenjun Su
IPC分类号： H03K19/094 , H03K3/00
CPC分类号： H03K19/01721 , H03K3/356017 , H03K19/018514
摘要： Differential signal output nodes of a novel CML buffer are DC-coupled by contiguous conductors to the differential signal input nodes of a load (for example, a CML logic element). The CML buffer includes a pulldown load latch that increases buffer transconductance and that provides a DC bias voltage across the conductors and onto the input nodes of the load, thereby obviating the need for the load to have DC biasing circuitry. Capacitors of a conventional AC coupling between buffer and load are not needed, thereby reducing the amount of die area needed to realize the circuit and thereby reducing the capacitance of the buffer-to-load connections. Switching power consumption is low due to the low capacitance buffer-to-load connections. Differential signals can be communicated from buffer to load over a wide frequency range of from less than five kilohertz to more than one gigahertz with less than fifty percent signal attenuation.
摘要翻译：新型CML缓冲器的差分信号输出节点通过连续的导体直接耦合到负载的差分信号输入节点（例如，CML逻辑元件）。 CML缓冲器包括下拉负载锁存器，其增加缓冲器跨导，并且在导体和负载的输入节点之间提供DC偏置电压，从而避免了负载需要DC偏置电路。不需要在缓冲器和负载之间的常规AC耦合的电容器，从而减少实现电路所需的管芯面积，从而减小缓冲器到负载连接的电容。由于低电容缓冲器到负载连接，开关功耗很低。差分信号可以从小于五千赫到宽达一千兆赫的宽频率范围内从缓冲器传送到负载，信号衰减小于百分之五十。

8. 发明授权

US09559639B2 Protection circuit for power amplifier 有权
标题翻译：功率放大器保护电路
公开(公告)号：US09559639B2
公开(公告)日：2017-01-31
申请号：US12715250
申请日：2010-03-01
申请人： Wenjun Su , Aristotele Hadjichristos , Gurkanwal S. Sahota , Marco Cassia
发明人： Wenjun Su , Aristotele Hadjichristos , Gurkanwal S. Sahota , Marco Cassia
IPC分类号： H04B1/04 , H03F1/52 , H03F3/24 , H03G3/30
CPC分类号： H03F1/52 , H03F3/24 , H03F2200/435 , H03F2200/78 , H03G3/3042 , H04B2001/0408
摘要： Techniques for protecting a power amplifier (PA) are described. In an exemplary design, an apparatus includes (i) a PA module to amplify an input RF signal and provide an output RF signal and (ii) a protection circuit to control a transmitter gain to protect the PA module against high peak voltage. In an exemplary design, the protection circuit includes a set of comparators to quantize an analog input signal and provide digital comparator output signals used to adjust the transmitter gain. In another exemplary design, the protection circuit reduces and increases the transmitter gain with hysteresis. In yet another exemplary design, the protection circuit has faster response to rising amplitude than falling amplitude of the output RF signal. The hysteresis and/or the different rise and fall responses may allow the protection circuit to avoid toggling the transmitter gain under severe load mismatch and to handle time-varying envelope due to amplitude modulation.
摘要翻译：描述了用于保护功率放大器（PA）的技术。在示例性设计中，装置包括（i）PA模块，用于放大输入RF信号并提供输出RF信号，以及（ii）保护电路以控制发射机增益以保护PA模块免受高峰值电压。在示例性设计中，保护电路包括一组比较器，用于量化模拟输入信号并提供用于调整发射机增益的数字比较器输出信号。在另一示例性设计中，保护电路通过滞后减小并增加发射机增益。在又一示例性设计中，保护电路比对输出RF信号的下降幅度具有对振幅上升的响应更快。迟滞和/或不同的上升和下降响应可以允许保护电路避免在严重负载不匹配的情况下切换发射机增益，并且由于幅度调制来处理时变包络。

9. 发明授权

US08310277B2 High linear fast peak detector 有权
标题翻译：高线性快速峰值检测器
公开(公告)号：US08310277B2
公开(公告)日：2012-11-13
申请号：US12718806
申请日：2010-03-05
申请人： Wenjun Su , Aristotele Hadjichristos , Marco Cassia , Chiewcharn Narathong
发明人： Wenjun Su , Aristotele Hadjichristos , Marco Cassia , Chiewcharn Narathong
IPC分类号： H03K5/153
CPC分类号： G01R19/04
摘要： A high linear fast peak detector having a variable bias current and/or a variable bias voltage is described. In an exemplary design, the peak detector includes a transistor, a variable current source, a capacitor, and a feedback circuit. The transistor receives the input signal and provides a source current. The variable current source receives the input signal, provides high bias current when the input signal is low, and provides low bias current when the input signal is high. The capacitor is charged by the source current when the input signal is high and is discharged by the high bias current when the input signal is low. The feedback circuit receives a detected signal from the capacitor and provides higher bias voltage for the transistor when the input signal is high, which results in higher source current from the transistor.
摘要翻译：描述具有可变偏置电流和/或可变偏置电压的高线性快速峰值检测器。在示例性设计中，峰值检测器包括晶体管，可变电流源，电容器和反馈电路。晶体管接收输入信号并提供源极电流。可变电流源接收输入信号，当输入信号为低电平时提供高偏置电流，并且当输入信号为高电平时提供低偏置电流。当输入信号为高电平时，电容器由电源电流充电，当输入信号为低电平时，电容器被高偏置电流放电。当输入信号为高电平时，反馈电路接收来自电容器的检测信号，并为晶体管提供较高的偏置电压，这导致来自晶体管的较高的源极电流。

10. 发明申请

US20110050285A1 HIGH LINEAR FAST PEAK DETECTOR 有权
标题翻译：高线性快速探测器
公开(公告)号：US20110050285A1
公开(公告)日：2011-03-03
申请号：US12718806
申请日：2010-03-05
申请人： Wenjun Su , Aristotele Hadjichristos , Marco Cassia , Chiewcham Narathong
发明人： Wenjun Su , Aristotele Hadjichristos , Marco Cassia , Chiewcham Narathong
IPC分类号： G01R19/04
CPC分类号： G01R19/04
摘要： A high linear fast peak detector having a variable bias current and/or a variable bias voltage is described. In an exemplary design, the peak detector includes a transistor, a variable current source, a capacitor, and a feedback circuit. The transistor receives the input signal and provides a source current. The variable current source receives the input signal, provides high bias current when the input signal is low, and provides low bias current when the input signal is high. The capacitor is charged by the source current when the input signal is high and is discharged by the high bias current when the input signal is low. The feedback circuit receives a detected signal from the capacitor and provides higher bias voltage for the transistor when the input signal is high, which results in higher source current from the transistor.
摘要翻译：描述具有可变偏置电流和/或可变偏置电压的高线性快速峰值检测器。在示例性设计中，峰值检测器包括晶体管，可变电流源，电容器和反馈电路。晶体管接收输入信号并提供源极电流。可变电流源接收输入信号，当输入信号为低电平时提供高偏置电流，并且当输入信号为高电平时提供低偏置电流。当输入信号为高电平时，电容器由电源电流充电，当输入信号为低电平时，电容器被高偏置电流放电。当输入信号为高电平时，反馈电路接收来自电容器的检测信号，并为晶体管提供更高的偏置电压，这导致来自晶体管的较高的源极电流。

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