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1. 发明授权

US08305752B2 Air duct and electronic device incorporating the same 失效
标题翻译：风管和包含其的电子装置
公开(公告)号：US08305752B2
公开(公告)日：2012-11-06
申请号：US12909824
申请日：2010-10-21
申请人： Chih-Wei Ke , Hao-Der Cheng
发明人： Chih-Wei Ke , Hao-Der Cheng
IPC分类号： H05K7/20 , F28F7/00
CPC分类号： H01L23/467 , G06F1/20 , H01L2924/0002 , H01L2924/00
摘要： An air duct defines a first air vent and a second air vent at opposite ends thereof, respectively. The air duct includes a duct body and a movable plate. The duct body defines a through opening in a side thereof. The through hole intercommunicates an interior and an exterior of the air duct. The movable plate is mounted on the side of the duct body adjacent to the through opening. By moving the movable plate, the through opening can be changed between an open state and a closed state freely. An electronic device incorporating the air duct is also provided.
摘要翻译：空气管道分别在其相对端分别形成第一通风口和第二通风口。风道包括管体和活动板。管体在其一侧限定通孔。通孔将空气管道的内部和外部相互连通。可移动板安装在与通孔相邻的管体的侧面。通过移动可动板，通孔可以在打开状态和关闭状态之间自由地改变。还提供了并入空气管道的电子设备。

2. 发明申请

US20100073048A1 PHASE LOCKED LOOP AND CALIBRATION METHOD 审中-公开
标题翻译：相位锁定和校准方法
公开(公告)号：US20100073048A1
公开(公告)日：2010-03-25
申请号：US12236725
申请日：2008-09-24
申请人： Ling-Wei KE , Tai-Yuan YU , Hsin-Hung CHEN , Tser-Yu LIN
发明人： Ling-Wei KE , Tai-Yuan YU , Hsin-Hung CHEN , Tser-Yu LIN
IPC分类号： H03L7/08
CPC分类号： H03L7/0898 , H03L7/093
摘要： A phase locked loop (PLL) directly uses a charge pump and loop filter therein for fast and low-costly calibration. The PLL comprises a charge pump, a loop filter, a voltage comparator, a counting device, and a calibration device. The loop filter comprises a voltage storage device coupled to the charge pump for charging by the charge pump, wherein the voltage storage device comprises a variable impedance. The voltage comparator is coupled to a voltage reference and to the voltage storage device for comparing a voltage of the storage device and a voltage of the voltage reference. The counting device is coupled to the voltage comparator to measure the charge time required for the voltage of the voltage storage device to substantially equal to the voltage of the voltage reference. The calibration device adjusts the variable impedance to adjust the time measured by the counting device to a desired time.
摘要翻译：锁相环（PLL）直接在其中使用电荷泵和环路滤波器，用于快速和低成本的校准。 PLL包括电荷泵，环路滤波器，电压比较器，计数装置和校准装置。环路滤波器包括耦合到电荷泵的电压存储装置，用于由电荷泵充电，其中电压存储装置包括可变阻抗。电压比较器耦合到电压基准和电压存储装置，用于比较存储装置的电压和电压基准的电压。计数装置耦合到电压比较器，以测量电压存储装置的电压所需的充电时间基本上等于电压基准的电压。校准装置调节可变阻抗，将计数装置测量的时间调整到所需的时间。

3. 发明申请

US20090130132A1 Anti-caveolin-1 polyclonal antibody, and antigen peptide sequence and method for preparing the same 有权
标题翻译：抗窖蛋白-1多克隆抗体和抗原肽序列及其制备方法
公开(公告)号：US20090130132A1
公开(公告)日：2009-05-21
申请号：US12081520
申请日：2008-04-17
申请人： Yu-Ten Ju , Jih-Tay Hsu , Yan-Nian Jiang , Meng-Wei Ke
发明人： Yu-Ten Ju , Jih-Tay Hsu , Yan-Nian Jiang , Meng-Wei Ke
IPC分类号： A61K39/00 , C07K16/18 , C07K14/00 , C12Q1/26 , G01N33/53 , G01N33/574
CPC分类号： C07K16/18 , C07K2317/33
摘要： The present invention provides a highly specific anti-Caveolin-1 polyclonal antibody, which is prepared by the following steps: (1) providing an antigen comprising a fragment of Caveolin-1 peptide sequence SEQ ID NO: 1; and (2) subcutaneously injecting said antigen into a rabbit to produce the anti-Caveolin-1 polyclonal antibody. The present invention also provides an antigen and a method used for preparing the anti-Caveolin-1 polyclonal antibody, and a kit used for detecting Caveolin-1 in a specimen.
摘要翻译：本发明提供高度特异性的抗窖蛋白-1多克隆抗体，其通过以下步骤制备：（1）提供包含窖蛋白-1肽序列SEQ ID NO：1的片段的抗原; 和（2）将所述抗原皮下注射入兔中以产生抗窖蛋白-1多克隆抗体。本发明还提供了用于制备抗窖蛋白-1多克隆抗体的抗原和方法，以及用于检测样品中窖蛋白-1的试剂盒。

4. 发明申请

US20090072911A1 SIGNAL GENERATING APPARATUS AND METHOD THEREOF 审中-公开
标题翻译：信号发生装置及其方法
公开(公告)号：US20090072911A1
公开(公告)日：2009-03-19
申请号：US11855161
申请日：2007-09-14
申请人： Ling-Wei Ke , Tai-Yuan Yu , Hsin-Hung Chen , Tser-Yu Lin
发明人： Ling-Wei Ke , Tai-Yuan Yu , Hsin-Hung Chen , Tser-Yu Lin
IPC分类号： H03L7/087 , H03L7/08 , H03L7/085
CPC分类号： H03L7/0898 , H03L7/087 , H03L7/113 , H03L7/18
摘要： A signal generating apparatus is disclosed. The signal generating apparatus includes a phase-locked loop device for generating a synthesized signal, wherein the phase-locked loop device includes a phase detector, a charge pump device, a filtering device, a controllable oscillator, and a switch device coupled to the controllable oscillator for selectively coupling the controllable oscillator to the filtering device or a tuning reference signal; a calibration controller generates a tuning reference signal and controls the switch device; and a first calibrator tunes the controllable oscillator into a predetermined sub-band according to a reference oscillating signal and a synthesized signal when the switch device couples the controllable oscillator to the tuning reference signal of the calibration controller.
摘要翻译：公开了一种信号发生装置。信号发生装置包括用于产生合成信号的锁相环装置，其中锁相环装置包括相位检测器，电荷泵装置，滤波装置，可控振荡器和耦合到可控制的开关装置用于选择性地将可控振荡器耦合到滤波装置的振荡器或调谐参考信号; 校准控制器产生调谐参考信号并控制开关装置; 并且当开关装置将可控振荡器耦合到校准控制器的调谐参考信号时，第一校准器根据参考振荡信号和合成信号将可控振荡器调谐成预定子带。

5. 发明授权

US07397227B2 Fast-disabled voltage regulator circuit with low-noise feedback loop and operating method thereof 有权
标题翻译：具有低噪声反馈回路的快速禁止稳压电路及其操作方法
公开(公告)号：US07397227B2
公开(公告)日：2008-07-08
申请号：US11383763
申请日：2006-05-17
申请人： Ling-Wei Ke , Chi-Kun Chiu
发明人： Ling-Wei Ke , Chi-Kun Chiu
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： A low-noise voltage regulator circuit with quick disablement includes an amplifier for outputting a driving voltage according to a reference voltage, a feedback voltage on a feedback node, and an enable signal; an output transistor coupled among the amplifier, an output node, and a first voltage source for outputting an output voltage at the output node; a first discharge transistor having a first size and coupled among the enable signal, the output node, and the feedback node; and a second discharge transistor having a second size being different than the first size and coupled among the enable signal, the feedback node, and a second voltage source; wherein when the enable signal disables the amplifier, the enable signal turns on the first discharge transistor and the second discharge transistor such that the output voltage is quickly pulled down to close a level provided by the second voltage source.
摘要翻译：具有快速禁用的低噪声电压调节器电路包括放大器，用于根据参考电压输出驱动电压，反馈节点上的反馈电压和使能信号; 耦合在所述放大器，输出节点和用于在所述输出节点处输出输出电压的第一电压源的输出晶体管; 第一放大晶体管，其具有第一尺寸并耦合在使能信号，输出节点和反馈节点之间; 以及第二放大晶体管，其具有与所述第一尺寸不同的第二尺寸，并且耦合在所述使能信号，所述反馈节点和第二电压源之间; 其中当使能信号禁用放大器时，使能信号使第一放电晶体管和第二放电晶体管导通，使得输出电压被快速下拉以接通由第二电压源提供的电平。

6. 发明申请

US20080003953A1 PHASE LOCKED LOOP FREQUENCY SYNTHESIZER AND METHOD FOR MODULATING THE SAME 有权
标题翻译：相位锁定频率合成器及其调制方法
公开(公告)号：US20080003953A1
公开(公告)日：2008-01-03
申请号：US11745611
申请日：2007-05-08
申请人： Ling-Wei Ke , Tai Yuan Yu , Hsin-Hung Chen
发明人： Ling-Wei Ke , Tai Yuan Yu , Hsin-Hung Chen
IPC分类号： H04B1/40
CPC分类号： H03L7/1976 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095
摘要： A phase locked loop frequency synthesizer including a phase locked loop, a frequency regenerator and a modulation processor, resistant to distortion induced by the frequency regenerator and conforming to transmission specifications. The phase locked loop comprises a detector generating a phase detection signal based on phase difference between a reference signal and a feedback signal, a loop filter, a voltage control oscillator generating a first output modulation signal and a frequency dividing unit varying a division factor based on a processed input modulation signal and dividing the frequency of the first output modulation signal by a division factor to generate the feedback signal. The frequency regenerator generates a second output modulation signal with a frequency range not overlapping an output frequency range of the voltage control oscillator. The modulation processor generates the processed input modulation signal to adjust the division factor of the frequency dividing unit and compensating for distortion induced by the frequency regenerator.
摘要翻译：一种锁相环频率合成器，包括锁相环，频率再生器和调制处理器，能够抵抗由频率再生器引起的失真并符合传输规范。锁相环包括检测器，其基于参考信号和反馈信号之间的相位差产生相位检测信号，环路滤波器，产生第一输出调制信号的电压控制振荡器和基于经处理的输入调制信号，并将第一输出调制信号的频率除以分频因子以产生反馈信号。频率再生器产生频率范围不与压控振荡器的输出频率范围重叠的第二输出调制信号。调制处理器产生经处理的输入调制信号，以调整分频单元的分频因子并补偿由频率再生器引起的失真。

7. 发明申请

US20060214651A1 FAST-DISABLED VOLTAGE REGULATOR CIRCUIT WITH LOW-NOISE FEEDBACK LOOP AND OPERATING METHOD THEREOF 有权
标题翻译：具有低噪声反馈环的快速禁止电压调节器电路及其工作方法
公开(公告)号：US20060214651A1
公开(公告)日：2006-09-28
申请号：US11383763
申请日：2006-05-17
申请人： Ling-Wei Ke , Chi-Kun Chiu
发明人： Ling-Wei Ke , Chi-Kun Chiu
IPC分类号： G05F3/04
CPC分类号： G05F1/575
摘要： A low-noise voltage regulator circuit with quick disablement includes an amplifier for outputting a driving voltage according to a reference voltage, a feedback voltage on a feedback node, and an enable signal; an output transistor coupled among the amplifier, an output node, and a first voltage source for outputting an output voltage at the output node; a first discharge transistor having a first size and coupled among the enable signal, the output node, and the feedback node; and a second discharge transistor having a second size being different than the first size and coupled among the enable signal, the feedback node, and a second voltage source; wherein when the enable signal disables the amplifier, the enable signal turns on the first discharge transistor and the second discharge transistor such that the output voltage is quickly pulled down to close a level provided by the second voltage source.
摘要翻译：具有快速禁用的低噪声电压调节器电路包括放大器，用于根据参考电压输出驱动电压，反馈节点上的反馈电压和使能信号; 耦合在所述放大器，输出节点和用于在所述输出节点处输出输出电压的第一电压源的输出晶体管; 第一放大晶体管，其具有第一尺寸并耦合在使能信号，输出节点和反馈节点之间; 以及第二放大晶体管，其具有与所述第一尺寸不同的第二尺寸，并且耦合在所述使能信号，所述反馈节点和第二电压源之间; 其中当使能信号禁用放大器时，使能信号使第一放电晶体管和第二放电晶体管导通，使得输出电压被快速下拉以接通由第二电压源提供的电平。

8. 发明申请

US20050058236A1 MULTI-MODULUS PROGRAMMABLE FREQUENCY DIVIDER 有权
标题翻译：多模式可编程分频器
公开(公告)号：US20050058236A1
公开(公告)日：2005-03-17
申请号：US10711410
申请日：2004-09-16
申请人： Ling-Wei Ke
发明人： Ling-Wei Ke
IPC分类号： H03K23/66 , H03K21/00
CPC分类号： H03K23/667
摘要： A programmable frequency divider for dividing the frequency of a source signal according to a selectable divisor which is obtained based on a plurality of divisor signals and outputting a result signal having a divided frequency includes at least one cell of a first type. The cells of the first type are cascaded with each other. The programmable frequency divider synchronously resets all of the cells of the first type according to a reset signal in order to selectively switch each cell of the first type to perform a divide-by-two or divide-by-three operation according to a corresponding divisor signal. The last cell of the first type outputs the result signal having the divided frequency.
摘要翻译：一种可编程分频器，用于根据基于多个除数信号获得的可选择除数来分频源信号的频率，并输出具有分频频率的结果信号包括至少一个第一类型的单元。第一类型的电池彼此级联。可编程分频器根据复位信号同步复位第一类型的所有单元，以选择性地切换第一类型的每个单元，以根据相应的除数进行二分频或三分频运算信号。第一类型的最后一个单元输出具有划分频率的结果信号。

9. 发明授权

US6054899A Automatic gain control circuit with low distortion 有权
标题翻译：自动增益控制电路具有低失真
公开(公告)号：US6054899A
公开(公告)日：2000-04-25
申请号：US236194
申请日：1999-01-22
申请人： Ling-Wei Ke
发明人： Ling-Wei Ke
IPC分类号： H03G1/00 , H03G3/10
CPC分类号： H03G1/007
摘要： An automatic gain control circuit is described, comprising: a resistance control node, a first field-effect transistor, a second field-effect transistor, an inductor, a first resistor, a second resistor, a first capacitor, and a second capacitor. The inductor is connected in series with the field-effect transistors. The first resistor is connected between the gate of the first field-effect transistor and the resistance control node while the second resistor is connected between the gate of the second field-effect transistor and the resistance control node. The first capacitor is connected between the gate and drain of the first field-effect transistor, whereas the second capacitor is connected between the gate and source of the second field-effect transistor.
摘要翻译：描述了一种自动增益控制电路，包括：电阻控制节点，第一场效应晶体管，第二场效应晶体管，电感器，第一电阻器，第二电阻器，第一电容器和第二电容器。电感器与场效晶体管串联连接。第一电阻器连接在第一场效应晶体管的栅极和电阻控制节点之间，而第二电阻器连接在第二场效应晶体管的栅极和电阻控制节点之间。第一电容器连接在第一场效应晶体管的栅极和漏极之间，而第二电容器连接在第二场效应晶体管的栅极和源极之间。

10. 发明授权

US09379059B2 Power and ground routing of integrated circuit devices with improved IR drop and chip performance 有权
标题翻译：集成电路器件的电源和接地布线具有改进的IR降低和芯片性能
公开(公告)号：US09379059B2
公开(公告)日：2016-06-28
申请号：US13286231
申请日：2011-11-01
申请人： Ching-Chung Ko , Tao Cheng , Tien-Yueh Liu , Ta-Hsi Chou , Peng-Cheng Kao , Ling-Wei Ke
发明人： Ching-Chung Ko , Tao Cheng , Tien-Yueh Liu , Ta-Hsi Chou , Peng-Cheng Kao , Ling-Wei Ke
IPC分类号： H01L27/10 , H01L23/528 , H01L21/8234
CPC分类号： H01L23/5286 , H01L21/823475 , H01L23/5226 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L2224/05124 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer.
摘要翻译：集成电路芯片包括其上具有多个IMD层和多个第一导电层的半导体衬底; 覆盖所述多个IMD层和所述第一导电层的第一钝化层; 在覆盖所述第一绝缘层的第一铝层中的至少第一电源/接地网布线; 以及覆盖在第一铝层上的第二铝层中的至少第二电源/接地网布线。

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