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1. 发明授权

US4706188A Method and apparatus for reading samples of a time-dependent signal in a data processing system 失效
标题翻译：用于在数据处理系统中读取时间相关信号的样本的方法和装置
公开(公告)号：US4706188A
公开(公告)日：1987-11-10
申请号：US698854
申请日：1985-02-06
申请人： Alois Rainer , Walter Ulbrich , Lajos Gazsi
发明人： Alois Rainer , Walter Ulbrich , Lajos Gazsi
IPC分类号： H03H15/00 , G06F3/05 , G06F17/10 , H03H17/02 , H03H21/00 , H04B3/04 , G06F12/02
CPC分类号： G06F3/05
摘要： A method and apparatus for preparing samples of a time-dependent signal (Se) in a data processing system which comprises an arithmetic unity (1), a control unit (2), a memory (3) and an address modification unit (13) wherein with a stored dataset of individual samples, for updating these step-by-step during every successive sampling period and respectively reading out the dated dataset and supplying it to the arithmetic unit (1), is achieved such that an address sequence which traverses a prescribed memory area is output via the address modification unit (13), so that a sequence of samples is written. Subsequently, the memory area is cyclically traversed with a plurality of address strings, whereby the stored samples are successively read out onto a bus line (4) and, when reaching an individual memory location within each of the address strings, the oldest sample stored there is overwritten by a further sample. The method is distinguished by a minimum of re-storing operations. The invention is used in signal processors, particularly those for filtering jobs.
摘要翻译：一种用于在包括算术单位（1），控制单元（2），存储器（3）和地址修改单元（13）的数据处理系统中准备时间相关信号（Se）的样本的方法和装置，其中利用存储的各个样本的数据集，用于在每个连续采样周期期间逐步更新这些数据集，并分别读出已注册的数据集并将其提供给算术单元（1），以使得经过通过地址修改单元（13）输出规定的存储区域，从而写入样本序列。随后，存储区域被循环地遍历多个地址串，由此存储的样本被连续地读出到总线（4）上，并且当到达每个地址串中的单个存储器位置时，存储在那里的最旧的样本被另一个样本覆盖。该方法通过最少的重新存储操作来区分。本发明用于信号处理器，特别是用于过滤作业的处理器。

2. 发明授权

US4675837A Digital arithmetic unit having shortened processing time and a simplified structure 失效
标题翻译：具有缩短处理时间和简化结构的数字运算单元
公开(公告)号：US4675837A
公开(公告)日：1987-06-23
申请号：US619185
申请日：1984-06-11
申请人： Walter Ulbrich , Alois Rainer , Tobias Noll
发明人： Walter Ulbrich , Alois Rainer , Tobias Noll
IPC分类号： G06F7/505 , G06F7/50 , G06F7/507 , G06F7/508 , G06F7/52
CPC分类号： G06F7/507
摘要： A digital arithmetic unit useful in data processing digital circuits comprises a plurality of stages each having two half-adders combined into a full adder and a carry logic element. An objective is to shorten the processing time for the addition and subtraction of binary numbers. For this purpose, the stages are divided into at least two groups and two separate carry paths are provided within each group. One of the carry paths is only switched on by means of selection logic elements. The activation occurs sequentially in group-wise fashion after simultaneous carry runs in all carry paths. The advantage particularly consists of the chronological coincidence of the carry runs in all groups.
摘要翻译：用于数据处理数字电路的数字运算单元包括多个级，每个级具有组合成全加器和进位逻辑元件的两个加法器。目的是缩短加法和减法二进制数的处理时间。为此，将这些阶段划分为至少两组，并在每组内提供两个单独的进位路径。其中一个进位路径仅通过选择逻辑元件接通。在所有携带路径中同时进行运行之后，以分组方式依次进行激活。这个优点特别包括所有组的进位运行的时间顺序。

3. 发明授权

US4819198A Saturable carry-save adder 失效
标题翻译：可靠的进位保存加法器
公开(公告)号：US4819198A
公开(公告)日：1989-04-04
申请号：US883657
申请日：1986-07-09
申请人： Tobias Noll , Walter Ulbrich
发明人： Tobias Noll , Walter Ulbrich
IPC分类号： G06F7/505 , G06F7/38 , G06F7/50 , G06F7/509 , G06F7/53
CPC分类号： G06F7/5095 , G06F7/49921
摘要： A carry-save adder for a bit-parallel addition of binary numbers in two's complement form incorporates a series of first adders for forming intermediate sum and carry words which are combined in an adder means to form a sum word. A decoder is provided for recognizing saturation of the carry-save adder and for generating overflow signals in dependence on the two most significant bits of the intermediate sum and carry words. When the overflow signals are generated, the recursive circuit branches are disconnected and saturation intermediate sum and carry words are substituted for the intermediate sum and carry words which yield sum words which do not exceed the permissible adder content.
摘要翻译：用于以二进制补码形式进行二进制数位位并行加法的进位保存加法器包括一系列用于形成中和和的乘法运算单元，它们在加法器装置中组合以形成和字。提供了一种解码器，用于识别进位保存加法器的饱和度，并且用于根据中间和和携带字的两个最高有效位产生溢出信号。当产生溢出信号时，递归电路分支断开，饱和中和和携带字代替中和和，并产生不超过允许加法器内容的和字。

4. 发明授权

US4839850A Apparatus for bit-parallel addition of binary numbers 失效
标题翻译：二进制数位位并行加法的装置
公开(公告)号：US4839850A
公开(公告)日：1989-06-13
申请号：US883942
申请日：1986-07-10
申请人： Tobias Noll , Walter Ulbrich
发明人： Tobias Noll , Walter Ulbrich
IPC分类号： G06F7/505 , G06F7/38 , G06F7/50 , G06F7/509 , G06F7/527 , G06F7/53
CPC分类号： G06F7/509 , G06F7/5095 , G06F7/4991
摘要： In an arrangement for the bit-parallel addition of binary numbers in two's complement form, a series of adders (AD.sub.i) are provided to receive inputs for binary bits of equivalent significance and to emit intermediate sum and carry words which are combined to form result sum words. For the correction of overflow errors, the carry bit of the adder (AD.sub.n-2) having the second highest significance is replaced by the carry bit of the most significant adder (AD.sub.n-1) and, when the carry bits of the two most significant adders (AD.sub.n-1, AD.sub.n-2) are unequal, the intermediate sum bit of the most significant adder (AD.sub.n-1) is replaced by its carry bit.
摘要翻译：在二进制补码形式中对二进制数位进行位并行加法的方案中，提供了一系列加法器（ADi），用于接收等效有效位的二进制位的输入，并发出中和和并携带相结合的字，形成结果和话。对于溢出错误的校正，具有第二高有效性的加法器（ADn-2）的进位位被最高有效加法器（ADn-1）的进位位代替，并且当两个最高有效位的进位位加法器（ADn-1，ADn-2）不相等，最高有效加法器（ADn-1）的中间和位由其进位位代替。

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