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    • 2. 发明申请
    • Method And System Of Energy-Efficient Control For Central Chiller Plant Systems
    • 中央冷冻机组系统节能控制方法与系统
    • US20110190946A1
    • 2011-08-04
    • US13060005
    • 2009-08-14
    • Charles Ho Yuen WongGang WuWillis Wai Yin Wong
    • Charles Ho Yuen WongGang WuWillis Wai Yin Wong
    • G05D23/19G06F1/28
    • F24F11/30F24F11/46F24F11/47F24F11/62
    • A method of energy-efficient control for central chiller plant systems includes the following steps: collecting performance characteristics of each piece of equipment in central chiller plant systems and establishing energy models for each piece of equipment in central chiller plant systems and establishing energy models for each piece of equipment according to performance characteristics; sampling, with a predetermined time interval, actual cooling load of central chiller plant systems, computing optimized system working conditions based on actual cooling load and energy models of each piece of equipment, wherein optimized system working conditions ensure the least global energy consumption of all of equipment in central chiller plant systems; adjusting working conditions for each piece of equipment according to optimized system working conditions; and repeating steps of collecting, sampling and adjusting. An energy-efficient control system for central chiller plant system is also disclosed.
    • 中央冷水机组系统的节能控制方法包括以下步骤:收集中央冷水机组系统中每件设备的性能特征,并为中央冷水机组系统中的每台设备建立能量模型,并为每个设备建立能量模型 一件设备根据性能特点; 以预定的时间间隔抽取中央冷水机组系统的实际冷负荷,根据每台设备的实际冷负荷和能量模型计算优化的系统工作条件,其中优化的系统工作条件确保全部能耗最小化 中央冷水机组系统设备; 根据优化的系统工作条件调整每台设备的工作条件; 并重复收集,采样和调整步骤。 还公开了一种用于中央冷水机组系统的节能控制系统。
    • 4. 发明授权
    • 4:2 compressor circuit for use in an arithmetic unit
    • 4:2用于运算单元的压缩机电路
    • US06711633B2
    • 2004-03-23
    • US10059607
    • 2002-01-30
    • Douglas Hooker BradleyTai Anh CaoRobert Alan PhilhowerWai Yin Wong
    • Douglas Hooker BradleyTai Anh CaoRobert Alan PhilhowerWai Yin Wong
    • G06F300
    • G06F7/607G06F7/5318
    • A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal. The sum circuit is configured to receive at least one of the control signals and further configured to generate a sum bit based at least in part on the state of the received control signal. At least one of the first stage, second stage, sum circuit, and carry circuit include at least one CMOS transmission gate comprised of an n-channel transistor and a p-channel transistor having their source/drain terminals connected in parallel, wherein the p-channel transistor gate is driven by the logical complement of the n-channel transistor gate. In one embodiment, the first stage, second stage, carry circuit, and sum circuit are comprised primarily of such transmission gates to the exclusion of conventional CMOS complementary passgate logic.
    • 适用于微处理器运算单元的压缩机电路包括第一级,第二级,进位电路和和电路。 第一级被配置为接收一组四个输入信号。 第一级产生指示第一对输入信号的XNOR的第一中间信号和指示第二对输入信号的XNOR的第二中间信号。 第二级被配置为接收由第一级产生的信号的至少一部分。 第二级产生第一和第二控制信号,其中第一控制信号指示四个输入信号的XNOR,第二控制信号是第一信号的逻辑补码。 进位电路被配置为接收至少一个控制信号,并且还被配置为至少部分地基于所接收的控制信号的状态来产生进位位。 总和电路被配置为接收至少一个控制信号,并且还被配置为至少部分地基于所接收的控制信号的状态来产生和位。 第一级,第二级,和电路和进位电路中的至少一个包括由n沟道晶体管和p沟道晶体管组成的至少一个CMOS传输门,其源极/漏极端子并联连接,其中p 通道晶体管栅极由n沟道晶体管栅极的逻辑补码驱动。 在一个实施例中,第一级,第二级,进位电路和和电路主要由这样的传输门组成,以排除常规CMOS互补门极逻辑。