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1. 发明授权

US08679929B2 On current in one-time-programmable memory cells 有权
标题翻译：关于一次可编程存储单元中的电流
公开(公告)号：US08679929B2
公开(公告)日：2014-03-25
申请号：US13312304
申请日：2011-12-06
申请人： Shanjen “Robert” Pan , Allan T. Mitchell , Weidong Tian
发明人： Shanjen “Robert” Pan , Allan T. Mitchell , Weidong Tian
IPC分类号： H01L21/336 , H01L21/425
CPC分类号： H01L21/28273 , H01L27/11206 , H01L27/11233 , H01L29/66825 , H01L29/7885
摘要： A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.
摘要翻译：一种在其编程状态之一制造具有改进的读取电流的一次性可编程（OTP）存储单元的方法，以及如此制造的存储单元。 OTP存储单元的侧面由沟槽隔离结构构成。在沟槽蚀刻之后，并且在用介电材料填充隔离沟槽之前，在沟槽表面中执行氟注入。植入物可能垂直于装置表面或与法线成一角度。然后完成单元晶体管以形成浮栅金属氧化物半导体（MOS）晶体管。来自氟植入物的改进的导通电流（Ion）。

2. 发明申请

US20130143375A1 On Current in One-Time-Programmable Memory Cells 有权
标题翻译：关于一次性可编程存储器单元中的电流
公开(公告)号：US20130143375A1
公开(公告)日：2013-06-06
申请号：US13312304
申请日：2011-12-06
申请人： Shanjen "Robert" Pan , Allan T. Mitchell , Weidong Tian
发明人： Shanjen "Robert" Pan , Allan T. Mitchell , Weidong Tian
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L27/11206 , H01L27/11233 , H01L29/66825 , H01L29/7885
摘要： A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.
摘要翻译：一种在其编程状态之一制造具有改进的读取电流的一次可编程（OTP）存储单元的方法，以及如此制造的存储器单元。 OTP存储单元的侧面由沟槽隔离结构构成。在沟槽蚀刻之后，并且在用介电材料填充隔离沟槽之前，在沟槽表面中执行氟注入。植入物可能垂直于装置表面或与法线成一角度。然后完成单元晶体管以形成浮栅金属氧化物半导体（MOS）晶体管。来自氟植入物的改进的导通电流（Ion）。

3. 发明申请

US20070057247A1 VERSATILE SYSTEM FOR CHARGE DISSIPATION IN THE FORMATION OF SEMICONDUCTOR DEVICE STRUCTURES 有权
标题翻译：用于形成半导体器件结构的充电放电的多元系统
公开(公告)号：US20070057247A1
公开(公告)日：2007-03-15
申请号：US11468648
申请日：2006-08-30
申请人： Weidong Tian , Bradley Sucher , Zafar Imam
发明人： Weidong Tian , Bradley Sucher , Zafar Imam
IPC分类号： H01L31/00
CPC分类号： H01L27/0248 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.
摘要翻译：本发明提供了一种用于消散在制造半导体器件段（200）期间可能累积的任何异常电荷的系统，消除过应力或分解对可能由于异常电荷的不受控耗散而导致的焦点设备结构（208）的损坏。衬底（202）具有设置在衬底顶部的第一和第二中间结构（204,206），其中焦点结构设置在衬底之上。第一导电结构（210）设置在第二中间结构，焦点结构和第一中间结构的一部分的顶部。第三中间结构（214）在第一导电结构和第一中间层的上方相邻地设置。在器件段的周边区域（218）中通过第一和第三中间层向下形成空隙（216）。第二导电结构（220）设置在第三中间结构的顶部，使得其通过空隙连接衬底。

4. 发明申请

US20060214170A1 VERSATILE SYSTEM FOR CHARGE DISSIPATION IN THE FORMATION OF SEMICONDUCTOR DEVICE STRUCTURES 有权
标题翻译：用于形成半导体器件结构的充电放电的多元系统
公开(公告)号：US20060214170A1
公开(公告)日：2006-09-28
申请号：US11420922
申请日：2006-05-30
申请人： Weidong Tian , Bradley Sucher , Zafar Imam
发明人： Weidong Tian , Bradley Sucher , Zafar Imam
IPC分类号： H01L29/76
CPC分类号： H01L27/0248 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.
摘要翻译：本发明提供了一种用于消散在制造半导体器件段（200）期间可能累积的任何异常电荷的系统，消除过应力或分解对可能由于异常电荷的不受控耗散而导致的焦点设备结构（208）的损坏。衬底（202）具有设置在衬底顶部的第一和第二中间结构（204,206），其中焦点结构设置在衬底之上。第一导电结构（210）设置在第二中间结构，焦点结构和第一中间结构的一部分的顶部。第三中间结构（214）在第一导电结构和第一中间层的上方相邻地设置。在器件段的周边区域（218）中通过第一和第三中间层向下形成空隙（216）。第二导电结构（220）设置在第三中间结构的顶部，使得其通过空隙连接衬底。

5. 发明申请

US20060033173A1 Versatile system for charge dissipation in the formation of semiconductor device structures 有权
公开(公告)号：US20060033173A1
公开(公告)日：2006-02-16
申请号：US10917763
申请日：2004-08-13
申请人： Weidong Tian , Bradley Sucher , Zafar Imam
发明人： Weidong Tian , Bradley Sucher , Zafar Imam
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L27/0248 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.

6. 发明授权

US08664706B2 Current in one-time-programmable memory cells 有权
标题翻译：一次可编程存储单元中的电流
公开(公告)号：US08664706B2
公开(公告)日：2014-03-04
申请号：US13528250
申请日：2012-06-20
申请人： Shanjen “Robert” Pan , Allan T. Mitchell , Weidong Tian
发明人： Shanjen “Robert” Pan , Allan T. Mitchell , Weidong Tian
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L21/28273 , H01L27/11206 , H01L27/11233 , H01L29/66825 , H01L29/7885
摘要： A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.
摘要翻译：一种在其编程状态之一制造具有改进的读取电流的一次可编程（OTP）存储单元的方法，以及如此制造的存储单元。 OTP存储单元的侧面由沟槽隔离结构构成。在沟槽蚀刻之后，并且在用介电材料填充隔离沟槽之前，在沟槽表面中执行氟注入。植入物可能垂直于装置表面或与法线成一角度。然后完成单元晶体管以形成浮栅金属氧化物半导体（MOS）晶体管。来自氟植入物的改进的导通电流（Ion）。

7. 发明申请

US20130065374A1 Fluorine Implant Under Isolation Dielectric Structures to Improve Bipolar Transistor Performance and Matching 有权
标题翻译：氟植入物隔离电介质结构提高双极晶体管性能和匹配
公开(公告)号：US20130065374A1
公开(公告)日：2013-03-14
申请号：US13451355
申请日：2012-04-19
申请人： Weidong Tian , Ming-Yeh Chuang , Rajni J. Aggarwal
发明人： Weidong Tian , Ming-Yeh Chuang , Rajni J. Aggarwal
IPC分类号： H01L21/331
CPC分类号： H01L29/732 , H01L29/1004 , H01L29/66272
摘要： A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch.
摘要翻译：一种制造包括双极晶体管的集成电路的方法，其降低了等离子体蚀刻期间由充电引起的晶体管性能下降和晶体管失配的影响，以及如此形成的集成电路。在形成隔离电介质之前，在要形成基极和发射极之间的隔离电介质结构的那些位置处进行氟注入。隔离电介质结构可以通过浅沟槽隔离来形成，其中氟注入在沟槽蚀刻之后进行，或LOCOS氧化，其中氟注入在热氧化之前进行。氟注入可以垂直于器件表面或与法线成一定角度。然后执行集成电路的完成，包括使用需要等离子体蚀刻的相对厚的铜金属化。

8. 发明授权

US07592252B2 Versatile system for charge dissipation in the formation of semiconductor device structures 有权
标题翻译：用于形成半导体器件结构的电荷耗散的通用系统
公开(公告)号：US07592252B2
公开(公告)日：2009-09-22
申请号：US11468648
申请日：2006-08-30
申请人： Weidong Tian , Bradley Sucher , Zafar Imam
发明人： Weidong Tian , Bradley Sucher , Zafar Imam
IPC分类号： H01L21/4763
CPC分类号： H01L27/0248 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.
摘要翻译：本发明提供了一种用于消散在制造半导体器件段（200）期间可能累积的任何异常电荷的系统，消除过应力或分解对可能由于异常电荷的不受控耗散而导致的焦点设备结构（208）的损坏。衬底（202）具有设置在衬底顶部的第一和第二中间结构（204,206），其中焦点结构设置在衬底之上。第一导电结构（210）设置在第二中间结构，焦点结构和第一中间结构的一部分的顶部。第三中间结构（214）在第一导电结构和第一中间层的上方相邻地设置。在器件段的周边区域（218）中通过第一和第三中间层向下形成空隙（216）。第二导电结构（220）设置在第三中间结构的顶部，使得其通过空隙连接衬底。

9. 发明申请

US20080277761A1 ON-CHIP ISOLATION CAPACITORS, CIRCUITS THEREFROM, AND METHODS FOR FORMING THE SAME 审中-公开
标题翻译：片上隔离电容器，其电路及其形成方法
公开(公告)号：US20080277761A1
公开(公告)日：2008-11-13
申请号：US12022877
申请日：2008-01-30
申请人： Pushpa Mahalingam , David C. Guiling , Sunny K. Lee , Ramon F. Figueroa , Weidong Tian , Yvonne D. Patton , Imran M. Khan
发明人： Pushpa Mahalingam , David C. Guiling , Sunny K. Lee , Ramon F. Figueroa , Weidong Tian , Yvonne D. Patton , Imran M. Khan
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L28/40 , H01G4/1272 , H01G4/33 , Y02T10/7022
摘要： An integrated circuit includes a substrate having a semiconducting surface, and at least one isolation capacitor on the surface. The capacitor includes a bottom electrically conductive plate in or on the surface, a multi-layer dielectric comprising stack over the bottom plate, and a top electrically conductive plate formed over the dielectric stack. The dielectric stack comprises at least one layer of silicon dioxide and at least one layer of silicon nitride, wherein the layer of silicon nitride is located immediately below or immediately above the top plate.
摘要翻译：集成电路包括具有半导体表面的衬底和表面上的至少一个隔离电容器。电容器包括位于表面中或表面上的底部导电板，在底板上包括堆叠的多层电介质，以及形成在电介质叠层上的顶部导电板。电介质堆叠包括至少一层二氧化硅和至少一层氮化硅，其中氮化硅层位于顶板的正下方或紧邻其上方。

10. 发明申请

US20080137262A1 Methods and systems for capacitors 审中-公开
标题翻译：电容器的方法和系统
公开(公告)号：US20080137262A1
公开(公告)日：2008-06-12
申请号：US11637283
申请日：2006-12-12
申请人： Pushpa Mahalingam , Alexander Wong , Marshall O. Cathey , Weidong Tian , Yvonne Dianne Patton , Joseph William Palmer , Billy Alan Wofford
发明人： Pushpa Mahalingam , Alexander Wong , Marshall O. Cathey , Weidong Tian , Yvonne Dianne Patton , Joseph William Palmer , Billy Alan Wofford
IPC分类号： H01G4/30 , H01G4/06 , H01G9/00
CPC分类号： H01G4/33 , H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention relates to a capacitor. The capacitor includes a first electrode and a capacitor dielectric layer along-side the first capacitor electrode. A second electrode is found along-side the capacitor dielectric layer includes a number of inter-layers that are configured to prevent defects in the second capacitor electrode. Other methods and devices are also disclosed.
摘要翻译：本发明的一个实施例涉及电容器。电容器包括沿着第一电容器电极的第一电极和电容器电介质层。沿着电容器电介质层的边缘发现第二电极包括被配置为防止第二电容器电极中的缺陷的多个层间层。还公开了其它方法和装置。

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