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1. 发明授权

US08189599B2 Omni-protocol engine for reconfigurable bit-stream processing in high-speed networks 有权
标题翻译：全速协议引擎，用于高速网络中的可重新配置的位流处理
公开(公告)号：US08189599B2
公开(公告)日：2012-05-29
申请号：US12862573
申请日：2010-08-24
申请人： Viswa Sharma , Roger Holschbach , Bart Stuck , William Chu
发明人： Viswa Sharma , Roger Holschbach , Bart Stuck , William Chu
IPC分类号： H04L12/56
CPC分类号： H04L69/18 , H04L69/12
摘要： A reconfigurable, protocol indifferent bit stream-processing engine, and related systems and data communication methodologies, are adapted to achieve the goal of providing inter-fabric interoperability among high-speed networks operating a speeds of at least 10 gigabits per second. The bit-stream processing engine operates as an omni-protocol, multi-stage processor that can be configured with appropriate switches and related network elements to create a seamless network fabric that permits interoperability not only among existing communication protocols, but also with the ability to accommodate future communication protocols. The method and systems of the present invention are applicable to networks that include storage networks, communication networks and processor networks.
摘要翻译：可重新配置的协议无关位流处理引擎以及相关的系统和数据通信方法适用于实现运行速度至少为每秒10吉比特的高速网络之间的架构间互操作性的目标。位流处理引擎作为一种全方位协议的多级处理器，可以配置适当的交换机和相关的网络元件，以创建无缝网络结构，不仅可以在现有的通信协议之间实现互操作，而且能够适应未来的通信协议。本发明的方法和系统适用于包括存储网络，通信网络和处理器网络的网络。

2. 发明申请

US20130007414A1 MULTI-CORE PROCESSOR APPARATUS WITH FLEXIBLE COMMUNICATION INTERCONNECTION 有权
标题翻译：具有灵活通信互连的多核处理器设备
公开(公告)号：US20130007414A1
公开(公告)日：2013-01-03
申请号：US13543882
申请日：2012-07-08
申请人： VISWA SHARMA
发明人： VISWA SHARMA
IPC分类号： G06F9/02
CPC分类号： G06F13/4022 , G06F13/382 , G06F13/4282 , G06F15/16 , H04L12/4625 , H04L12/56
摘要： A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.
摘要翻译：提供了一种计算和通信芯片架构，其中处理器访问存储器芯片的接口被实现为作为每个芯片的一部分的高速分组交换串行接口。在一个实施例中，通过集成为芯片的一部分的协议处理器提供的千兆位以太网接口来实现接口。协议处理器将存储器地址和控制信息（如读取，写入，连续字节数等）封装为用于处理器和位于同一主板上的存储器芯片之间或甚至在不同电路卡上的通信的以太网分组。在一个实施例中，通过在受约束的邻域内使用具有缩短的数据帧的增强型以太网协议和/或通过利用比特流交换机来进一步减少以太网协议头上的通信，其中可以在包括的元素之间建立直接连接路径计算或通信架构。

3. 发明申请

US20080244150A1 PROCESSOR CHIP ARCITECTURE HAVING INTEGRATED HIGH-SPEED PACKET SWITCHED SERIAL INTERFACE 有权
标题翻译：具有集成高速分组交换串行接口的处理器芯片ARCITECTURE
公开(公告)号：US20080244150A1
公开(公告)日：2008-10-02
申请号：US12025720
申请日：2008-02-04
申请人： Viswa Sharma
发明人： Viswa Sharma
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/382 , G06F13/4282 , G06F15/16 , H04L12/4625 , H04L12/56
摘要： A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.
摘要翻译：提供了一种计算和通信芯片架构，其中处理器访问存储器芯片的接口被实现为作为每个芯片的一部分的高速分组交换串行接口。在一个实施例中，通过集成为芯片的一部分的协议处理器提供的千兆位以太网接口来实现接口。协议处理器将存储器地址和控制信息（如读取，写入，连续字节数等）封装为用于处理器和位于同一主板上的存储器芯片之间或甚至在不同电路卡上的通信的以太网分组。在一个实施例中，通过在受约束的邻域内使用具有缩短的数据帧的增强型以太网协议和/或通过利用比特流交换机来进一步减少以太网协议头上的通信，其中可以在包括的元素之间建立直接连接路径计算或通信架构。

4. 发明申请

US20080037218A1 Modular chassis providing scalable mechanical, electrical and environmental functionality for MicroTCA and advanced TCA boards 有权
标题翻译：模块化机箱为MicroTCA和高级TCA板提供可扩展的机械，电气和环境功能
公开(公告)号：US20080037218A1
公开(公告)日：2008-02-14
申请号：US11728718
申请日：2007-03-26
申请人： Viswa Sharma , William Chu , Allen James , Ming Tseng , Neil Schlegel , David Lentz , Christopher Sonnek
发明人： Viswa Sharma , William Chu , Allen James , Ming Tseng , Neil Schlegel , David Lentz , Christopher Sonnek
IPC分类号： H05K7/20 , H05K5/00
CPC分类号： H05K7/1424
摘要： A modular chassis arrangement for electronic modules that is configurable into a mechanically and electrically interconnected structure capable of delivering scalable mechanical, electrical and environmental functionality for a multiplicity of electronic modules. In one embodiment, the electronic modules are compliant with AdvancedTCA or MicroTCA standards in a modular Pico-Shelf configuration that support stackable and/or back-to-back multiple unit chassis.
摘要翻译：一种用于电子模块的模块化底盘装置，其可配置成机械和电气互连的结构，能够为多个电子模块提供可伸缩的机械，电气和环境功能。在一个实施例中，电子模块符合支持可堆叠和/或背靠背多单元机箱的模块化Pico-Shelf配置中的AdvancedTCA或MicroTCA标准。

5. 发明授权

US07822946B2 On-chip packet interface processor encapsulating memory access from main processor to external system memory in serial packet switched protocol 有权
标题翻译：片上分组接口处理器封装从主处理器到串行分组交换协议中的外部系统存储器的存储器访问
公开(公告)号：US07822946B2
公开(公告)日：2010-10-26
申请号：US12025720
申请日：2008-02-04
申请人： Viswa Sharma
发明人： Viswa Sharma
IPC分类号： G06F13/14
CPC分类号： G06F13/4022 , G06F13/382 , G06F13/4282 , G06F15/16 , H04L12/4625 , H04L12/56
摘要： A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.
摘要翻译：提供了一种计算和通信芯片架构，其中处理器访问存储器芯片的接口被实现为作为每个芯片的一部分的高速分组交换串行接口。在一个实施例中，通过集成为芯片的一部分的协议处理器提供的千兆位以太网接口来实现接口。协议处理器将存储器地址和控制信息（如读取，写入，连续字节数等）封装为用于处理器和位于同一主板上的存储器芯片之间或甚至在不同电路卡上的通信的以太网分组。在一个实施例中，通过在受约束的邻域内使用具有缩短的数据帧的增强型以太网协议和/或通过利用比特流交换机来进一步减少以太网协议头上的通信，其中可以在包括的元素之间建立直接连接路径计算或通信架构。

6. 发明授权

US07782873B2 Omni-protocol engine for reconfigurable bit-stream processing in high-speed networks 有权
标题翻译：全速协议引擎，用于高速网络中的可重新配置的位流处理
公开(公告)号：US07782873B2
公开(公告)日：2010-08-24
申请号：US11466367
申请日：2006-08-22
申请人： Viswa Sharma , Roger Holschbach , Bart Stuck , William Chu
发明人： Viswa Sharma , Roger Holschbach , Bart Stuck , William Chu
IPC分类号： H04L12/56
CPC分类号： H04L69/18 , H04L69/12
摘要： A reconfigurable, protocol indifferent bit stream-processing engine, and related systems and data communication methodologies, are adapted to achieve the goal of providing inter-fabric interoperability among high-speed networks operating a speeds of at least 10 gigabits per second. The bit-stream processing engine operates as an omni-protocol, multi-stage processor that can be configured with appropriate switches and related network elements to create a seamless network fabric that permits interoperability not only among existing communication protocols, but also with the ability to accommodate future communication protocols. The method and systems of the present invention are applicable to networks that include storage networks, communication networks and processor networks.
摘要翻译：可重新配置的协议无关位流处理引擎以及相关的系统和数据通信方法适用于实现运行速度至少为每秒10吉比特的高速网络之间的架构间互操作性的目标。位流处理引擎作为一种全方位协议的多级处理器，可以配置适当的交换机和相关的网络元件，以创建无缝网络结构，不仅可以在现有的通信协议之间实现互操作，而且能够适应未来的通信协议。本发明的方法和系统适用于包括存储网络，通信网络和处理器网络的网络。

7. 发明申请

US20090097200A1 MODULAR BLADE FOR PROVIDING SCALABLE MECHANICAL, ELECTRICAL AND ENVIRONMENTAL FUNCTIONALITY IN THE ENTERPRISE USING ADVANCEDTCA BOARDS 审中-公开
标题翻译：使用高级电路板在企业中提供可扩展的机械，电气和环境功能的模块式刀片
公开(公告)号：US20090097200A1
公开(公告)日：2009-04-16
申请号：US12101739
申请日：2008-04-11
申请人： Viswa Sharma , William Chu
发明人： Viswa Sharma , William Chu
IPC分类号： H05K7/00 , H05K7/20
CPC分类号： G06F1/18 , G06F1/183 , G06F1/20 , H05K7/1487
摘要： A standards-based server blade arrangement is provided wherein individual circuit boards may be compliant with a first industry driven or other standard and housed within an enclosure configured such that one aspect of the enclosure provides each circuit board with a scalable, mechanical, electrical and environmental functionality required for that circuit board to comply with the first industry driven or other standard and a second aspect of the enclosure allows the enclosure to comply with a second industry driven or other standard.
摘要翻译：提供了一种基于标准的服务器刀片布置，其中单独的电路板可以符合第一工业驱动或其他标准并且容纳在外壳内，其被配置为使得外壳的一个方面为每个电路板提供可伸缩的，机械的，电气的和环境的该电路板符合第一个工业驱动或其他标准所需的功能，另一个方面的外壳允许外壳符合第二个工业驱动或其他标准。

8. 发明申请

US20080052436A1 TELECOMMUNICATION AND COMPUTING PLATFORMS WITH SERIAL PACKET SWITCHED INTEGRATED MEMORY ACCESS TECHNOLOGY 有权
标题翻译：具有串行分组交换式集成存储器访问技术的电信和计算机平台
公开(公告)号：US20080052436A1
公开(公告)日：2008-02-28
申请号：US11828329
申请日：2007-07-25
申请人： Viswa Sharma , Barton Stuck , Ching-Tao Hu , Yi-chang Chou , William Chu
发明人： Viswa Sharma , Barton Stuck , Ching-Tao Hu , Yi-chang Chou , William Chu
IPC分类号： G06F13/00
CPC分类号： G06F13/4063
摘要： A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.
摘要翻译：计算和通信架构在包装布置中的电路卡之间使用基于串行协议的交换结构。在一个实施例中，在封装装置中连接到基于串行协议的交换结构的每个电路卡设置有协议处理器，其使得所有电路卡能够以线速度有效地提供基于分组的串行自定时通信。结果，不需要以分层方式布置电路卡，以便解决交换机阻塞和相关业务拥塞问题的问题，否则将限制基于串行协议的背板布置用于容纳电路卡的实现。

9. 发明申请

US20070067481A1 OMNI-PROTOCOL ENGINE FOR RECONFIGURABLE BIT-STREAM PROCESSING IN HIGH-SPEED NETWORKS 有权
标题翻译： OMNI-PROTOCOL发动机用于高速网络中的可重新配置的位流处理
公开(公告)号：US20070067481A1
公开(公告)日：2007-03-22
申请号：US11466367
申请日：2006-08-22
申请人： Viswa Sharma , Roger Holschbach , Bart Stuck , William Chu
发明人： Viswa Sharma , Roger Holschbach , Bart Stuck , William Chu
IPC分类号： G06F15/16
CPC分类号： H04L69/18 , H04L69/12
摘要： A reconfigurable, protocol indifferent bit stream-processing engine, and related systems and data communication methodologies, are adapted to achieve the goal of providing inter-fabric interoperability among high-speed networks operating a speeds of at least 10 gigabits per second. The bit-stream processing engine operates as an omni-protocol, multi-stage processor that can be configured with appropriate switches and related network elements to create a seamless network fabric that permits interoperability not only among existing communication protocols, but also with the ability to accommodate future communication protocols. The method and systems of the present invention are applicable to networks that include storage networks, communication networks and processor networks.
摘要翻译：可重新配置的协议无关位流处理引擎以及相关的系统和数据通信方法适用于实现运行速度至少为每秒10吉比特的高速网络之间的架构间互操作性的目标。位流处理引擎作为一种全方位协议的多级处理器，可以配置适当的交换机和相关的网络元件，以创建无缝网络结构，不仅可以在现有的通信协议之间实现互操作，而且能够适应未来的通信协议。本发明的方法和系统适用于包括存储网络，通信网络和处理器网络的网络。

10. 发明授权

US07136397B2 Network architecture and system for delivering bi-directional xDSL based services 有权
公开(公告)号：US07136397B2
公开(公告)日：2006-11-14
申请号：US10223832
申请日：2002-08-19
申请人： Viswa Sharma
发明人： Viswa Sharma
IPC分类号： H04J1/02
CPC分类号： H04L12/2865 , H04L12/2856 , H04M11/062 , Y02D50/30
摘要： A simple network comprises of: xDSL service equipment located at a distribution center coupled to an Aggregator Separator (AGSEP) System located at a DC; AGSEP system at the DC is coupled, using a high-speed link, to another AGSEP system located at a remote site, which is coupled to subscriber equipment using drop cables. The AGSEP systems aggregate the xDSL signals originating at either DC xDSL equipment or subscriber equipment, are carried over the high-speed link. The AGSEP systems and separate the aggregated signals at either end to distribute the separated signal to the respective equipment.

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