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1. 发明申请

US20060075371A1 Method and system for semiconductor design hierarchy analysis and transformation 有权
公开(公告)号：US20060075371A1
公开(公告)日：2006-04-06
申请号：US10955067
申请日：2004-09-30
申请人： Vishnu Kamat
发明人： Vishnu Kamat
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068
摘要： A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.

2. 发明申请

US20060075379A1 Method and system for managing design corrections for optical and process effects based on feature tolerances 有权
标题翻译：基于特征公差管理光学和过程效果的设计校正的方法和系统
公开(公告)号：US20060075379A1
公开(公告)日：2006-04-06
申请号：US10955527
申请日：2004-09-30
申请人： Vishnu Kamat
发明人： Vishnu Kamat
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for modifying instances of a repeating pattern in an integrated circuit design to correct for perturbations during rendering is described. In the typical embodiment, these corrections are optical proximity corrections that correct for optical effects during the projection of the mask pattern onto the wafer and/or processing effects for example photoresist response and etching effects. The method comprises determining a correction for the repeating pattern based on a first set of tolerances for features of the repeating pattern. Then, the suitability of the corrections is evaluated for instances of the repeating pattern in the integrated circuit design based on a second set of tolerances, which is different from the first set of tolerances. This can be used to preserve much of the hierarchy of the layout data in the corrected, or lithography, data. This can be achieved during the OPC process, thus avoiding the post OPC compaction. It can further take advantage of the fact that, for a given physical layer of a chip for example, different portions of the representing design polygons typically have different requirements on pattern fidelity on the wafer while perturbations may vary as a function of field position. By applying knowledge of the feature tolerances, and allowing design corrections only when tolerances are not met, the data explosion that occurs when moving from layout to lithography data can be contained without sacrificing accuracy.
摘要翻译：描述了在集成电路设计中修改重复图案的实例以校正渲染期间的扰动的方法。在典型的实施例中，这些校正是在掩模图案投影到晶片上和/或处理效果例如光致抗蚀剂响应和蚀刻效果时校正光学效果的光学邻近校正。该方法包括基于重复图案的特征的第一组公差来确定针对重复图案的校正。然后，基于与第一组公差不同的第二组公差，对集成电路设计中的重复图案的实例进行校正的适用性。这可以用于保留校正或光刻数据中布局数据的大部分层次。这可以在OPC过程中实现，从而避免后OPC压缩。可以进一步利用以下事实：对于给定的芯片的物理层，例如，表示设计多边形的不同部分通常对晶片上的图案保真度具有不同的要求，同时扰动可以随现场位置的函数而变化。通过应用特征公差的知识，并且只有在不满足公差的情况下才能进行设计校正，可以在不牺牲精度的情况下包含从布局移动到光刻数据时发生的数据爆炸。

3. 发明申请

US20050273734A1 Correcting design data for manufacture 有权
标题翻译：校正设计数据进行制造
公开(公告)号：US20050273734A1
公开(公告)日：2005-12-08
申请号：US10860852
申请日：2004-06-04
申请人： Vishnu Kamat
发明人： Vishnu Kamat
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method of correction for design data includes the steps of sequentially applying a plurality of corrections to a plurality of features based on a plurality of feature tolerances to design data in a predetermined order, and providing corrected design data.
摘要翻译：一种用于设计数据的校正方法包括以下步骤：基于多个特征公差，以预定顺序设计数据，并提供校正后的设计数据，将多个校正顺序地应用于多个特征。

4. 发明申请

US20070160917A1 Correcting 3D Effects In Phase Shifting Masks Using Sub-Resolution Features 有权
标题翻译：使用子分辨率功能校正相移掩码中的3D效果
公开(公告)号：US20070160917A1
公开(公告)日：2007-07-12
申请号：US11462686
申请日：2006-08-04
申请人： Vishnu Kamat , Armen Kroyan
发明人： Vishnu Kamat , Armen Kroyan
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/30 , G03F1/36
摘要： Using phase shifting on a mask can advantageously improve printed feature resolution on a wafer, thereby allowing greater feature density on an integrated circuit. Phase shifting can create an intensity imbalance between 0 degree and 180 degree phase shifters on the mask. An improved method of designing an alternating PSM to minimize this intensity imbalance is provided. Sub-resolution features, called “blockers”, can be incorporated in the alternating PSM design. Specifically, blockers can be formed in the 0 degree phase shifters. In this configuration, the intensity associated with the 0 degree phase shifters approximates the intensity associated with the corresponding 180 degree phase shifters. Intensity balancing using blockers retains image contrast, thereby ensuring printed feature quality.
摘要翻译：使用掩模上的相移可以有利地提高晶片上的印刷特征分辨率，从而允许集成电路上的更大的特征密度。相移可能在掩模上产生0度和180度移相器之间的强度不平衡。提供了一种设计交替PSM以最小化该强度不平衡的改进方法。称为“阻塞剂”的亚分辨率特征可以并入交替的PSM设计中。具体地，可以在0度移相器中形成阻挡剂。在该配置中，与0度移相器相关联的强度近似于与相应的180度移相器相关联的强度。使用阻滞剂的强度平衡保留了图像对比度，从而确保打印的特征质量。

5. 发明申请

US20050177809A1 Correcting 3D effects in phase shifting masks using sub-resolution features 有权
标题翻译：使用子分辨率特征校正相移掩模中的3D效果
公开(公告)号：US20050177809A1
公开(公告)日：2005-08-11
申请号：US10774342
申请日：2004-02-05
申请人： Vishnu Kamat , Armen Kroyan
发明人： Vishnu Kamat , Armen Kroyan
IPC分类号： G03F1/00 , G06F17/50
CPC分类号： G03F1/30 , G03F1/36
摘要： Using phase shifting on a mask can advantageously improve printed feature resolution on a wafer, thereby allowing greater feature density on an integrated circuit. Phase shifting can create an intensity imbalance between 0 degree and 180 degree phase shifters on the mask. An improved method of designing an alternating PSM to minimize this intensity imbalance is provided. Sub-resolution features, called “blockers”, can be incorporated in the alternating PSM design. Specifically, blockers can be formed in the 0 degree phase shifters. In this configuration, the intensity associated with the 0 degree phase shifters approximates the intensity associated with the corresponding 180 degree phase shifters. Intensity balancing using blockers retains image contrast, thereby ensuring printed feature quality.
摘要翻译：使用掩模上的相移可以有利地提高晶片上的印刷特征分辨率，从而允许集成电路上的更大的特征密度。相移可能在掩模上产生0度和180度移相器之间的强度不平衡。提供了一种设计交替PSM以最小化该强度不平衡的改进方法。称为“阻塞剂”的亚分辨率特征可以并入交替的PSM设计中。具体地，可以在0度移相器中形成阻挡剂。在该配置中，与0度移相器相关联的强度近似于与相应的180度移相器相关联的强度。使用阻滞剂的强度平衡保留了图像对比度，从而确保打印的特征质量。

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