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1. 发明授权

US5798717A One-hot overflow matrix with enhanced architecture and one-hot variable length decoder incorporating the same 失效
标题翻译：具有增强架构的单热溢出矩阵和包含其的一热可变长度解码器
公开(公告)号：US5798717A
公开(公告)日：1998-08-25
申请号：US671891
申请日：1996-06-28
申请人： Michael Bakhmutsky , Viktor L. Gornstein
发明人： Michael Bakhmutsky , Viktor L. Gornstein
IPC分类号： H03M7/42 , H03M7/40
CPC分类号： H03M7/425
摘要： A one-hot overflow matrix which includes a first one-hot input comprised of a plurality n of parallel bits arranged in sequence from a zero bit position to an (n-1) bit position, a second one-hot input comprised of a plurality n of parallel bits arranged in sequence from a zero bit position to an (n-1) bit position, a plurality n of output gates (e.g., tri-state buffers) each having a first input, a second input, and an output, a data output line commonly coupled to the output of each of the output gates, a plurality n/2 of NOR gates each having one or more data inputs, and a data output, and a plurality (n/2-1) of OR gates each having one or more data inputs, and a data output. The data input(s) of each respective ith one of the NOR gates are respectively coupled to the zero bit position through ((n-1)-i) bit position bit(s) of the second one-hot input. The first input of each respective ith one of the output gates is coupled to the data output of a corresponding ith one of the NOR gates, and the second input of each respective ith one of the output gates is coupled to a corresponding ith bit position bit of the first one-hot input. The data input(s) of each respective jth one of the OR gates are respectively coupled to the (n-j) bit position through (n-1) bit position bits of the second one-hot input, where i=n/2 through (n-1), and j=(n/2-1) through 1.
摘要翻译：一个热溢出矩阵，其包括由从零位位置到（n-1）位位置顺序排列的多个并行位数组成的第一单热输入，第二单热输入，包括多个 n个从零位位置到（n-1）位位置顺序排列的并行位，多个n个输出门（例如，三态缓冲器），每个具有第一输入，第二输入和输出，通常耦合到每个输出门的输出的数据输出线，每个具有一个或多个数据输入的多个n / 2个或非门，以及数据输出，以及多个（n / 2-1）个或门每个具有一个或多个数据输入和数据输出。每个第一个或非门中的每一个的数据输入分别通过第二单热输入的（（n-1）-i）位位置位耦合到零位位置。每个输出门中的每一个的第一输入被耦合到对应的第一个或非门之一的数据输出，并且每个第一个输出门的每一个的第二输入被耦合到对应的第i个位位的第一个热输入。每个或者第一个或门的数据输入分别通过第二单热输入的（n-1）位位置位耦合到（nj）位位置，其中i = n / 2到（ n-1），j =（n / 2-1）〜1。

2. 发明授权

US5767917A Method and apparatus for multi-standard digital television synchronization 失效
标题翻译：用于多标准数字电视同步的方法和装置
公开(公告)号：US5767917A
公开(公告)日：1998-06-16
申请号：US643068
申请日：1996-04-30
申请人： Viktor L. Gornstein , Alan P. Cavallerano
发明人： Viktor L. Gornstein , Alan P. Cavallerano
IPC分类号： H04N5/04 , H04L1/00 , H04L7/027 , H04L29/08 , H04N5/06 , H04N5/08 , H04N5/44 , H04N5/46 , H04N7/56
CPC分类号： H04N5/08 , H04N5/46 , H04N7/56 , H04N7/012
摘要： An apparatus for automatically synchronizing a video system to one of a plurality of composite synchronizing signals in accordance with a plurality of known video formats, includes a number of synchronizing signal stripper circuits, corresponding, respectively, to a number of types of composite synchronizing signals, a horizontal analyzer, having a plurality of horizontal standard identification circuits corresponding to a identification circuits for each known horizontal synchronizing signal rate for each type of composite synchronizing signal, for determining an approximate horizontal synchronizing signal rate and, a vertical analyzer, having a plurality of vertical rate identification circuits corresponding to the number of different known vertical rates, for determining the vertical synchronizing signal rate.
摘要翻译：一种用于根据多种已知视频格式将视频系统自动同步到多个复合同步信号之一的装置包括分别对应于多种类型的复合同步信号的多个同步信号分离器电路，水平分析器，具有多个水平标准识别电路，对应于用于每种类型的复合同步信号的每个已知的水平同步信号速率的识别电路，用于确定近似的水平同步信号速率;以及垂直分析仪，具有多个对应于不同已知垂直速率数量的垂直速率识别电路，用于确定垂直同步信号速率。

3. 发明授权

US07689637B1 Adaptive filtering method and related device 失效
标题翻译：自适应滤波方法及相关设备
公开(公告)号：US07689637B1
公开(公告)日：2010-03-30
申请号：US09564427
申请日：2000-05-04
申请人： Viktor L. Gornstein , Gennady Turkenich
发明人： Viktor L. Gornstein , Gennady Turkenich
IPC分类号： G06F17/10
CPC分类号： H03H21/0043
摘要： An input signal is filtered for creating an output signal using an adaptive filter. An error signal is derived from the output signal. The adaptive filter has coefficient whose value can be modified. A value of a coefficient is modified using a derived updating amount. The updating amount is obtained from the product of a value of the input signal, a value of the polarity of the error signal, and a step gain. The step gain has the form 2K with K being an integer and being dependent on a magnitude of the value of the error signal and on a step gain parameter. The updating amount is dependent on both the magnitude and the polarity of the error signal, therefore allowing a precise update of the coefficient. The specific form of the step gain allows a fast derivation of the product.
摘要翻译：对输入信号进行滤波，以使用自适应滤波器产生输出信号。从输出信号导出误差信号。自适应滤波器的值可以被修改。使用导出的更新量来修改系数的值。从输入信号的值，误差信号的极性的值和阶跃增益的乘积得到更新量。阶梯增益具有2K的形式，其中K是整数，并且取决于误差信号的值的大小和阶跃增益参数。更新量取决于误差信号的幅度和极性，从而允许精确地更新系数。阶梯增益的具体形式允许快速推导产品。

4. 发明授权

US06734868B2 Address generator for video pixel reordering in reflective LCD 失效
标题翻译：地址发生器用于反射LCD中的视频像素重排序
公开(公告)号：US06734868B2
公开(公告)日：2004-05-11
申请号：US10028380
申请日：2001-12-21
申请人： Viktor L. Gornstein , John E. Dean
发明人： Viktor L. Gornstein , John E. Dean
IPC分类号： G06F1206
CPC分类号： G09G3/20 , G09G2310/0221 , G09G2310/0297 , G09G2352/00
摘要： An address generator for a pixel shuffler used in a relective liquid crystal display (RLCD) digital video system, and a pixel shuffler incorporating such an address generator. The address generator includes a small, dual port SRAM 160×8, a combinatorial converter having a pair of inputs and an output representing a predetermined relationship of the inputs, a pixel counter with a pair of decoders, a line counter, a computing block for selectively implementing a mirror reflection of the pixel addresses, as well as a plurality of D flip flops and logic elements. The pixel shuffler operates in read-modify-write mode, whereby any address location of memory is read and immediately overwritten with the new data. This permits operation with only one bank of SRAM 320×96 rather than the customary two banks for prior art pixel shufflers using the so-called Ping Pong method.
摘要翻译：用于反射型液晶显示器（RLCD）数字视频系统中的像素洗牌器的地址发生器，以及包含这样的地址发生器的像素洗牌器。地址发生器包括一个小的双端口SRAM 160x8，组合转换器，具有一对输入和表示输入的预定关系的输出，具有一对解码器的像素计数器，行计数器，用于选择性地执行的计算块像素地址的镜像反射，以及多个D触发器和逻辑元件。像素洗牌器以读 - 修改 - 写入模式运行，从而读取存储器的任何地址位置并立即用新数据覆盖。这允许使用所谓的乒乓方法仅使用一行SRAM 320x96而不是现有技术的像素洗牌器的常规两个组。

5. 发明授权

US06360015B1 RAM-based search engine for orthogonal-sum block match motion estimation system 有权
标题翻译：基于RAM的搜索引擎，用于正交和块匹配运动估计系统
公开(公告)号：US06360015B1
公开(公告)日：2002-03-19
申请号：US09287165
申请日：1999-04-06
申请人： Michael Bakhmutsky , Viktor L. Gornstein
发明人： Michael Bakhmutsky , Viktor L. Gornstein
IPC分类号： G06K900
CPC分类号： H04N19/59 , H04N19/43 , H04N19/51
摘要： A RAM-based search engine for updating a horizontal sum representing the sum of the values of N pixels contained in a horizontal row of a reference pixel array during a motion estimation search during which the reference pixel array is displaced by one pixel in a horizontal search direction during each of a plurality of iterations of the motion estimation search. The RAM-based search engine includes a horizontal sum modifier circuit that accumulates the values of the N pixels contained in the horizontal row of the reference pixel array prior to any displacement of the reference pixel array to produce the horizontal sum, and that updates the horizontal sum by computing the new horizontal sum using the following equation: OSNEW=OSOLD−a00+ano, where OSNEW is the new horizontal sum after the last displacement of the reference pixel array by one pixel in the horizontal direction, OSOLD is the horizontal sum prior to the last displacement of the reference pixel array by one pixel in the horizontal direction, a00 is the pixel value of the pixel that was the horizontal origin of the reference pixel array prior to the last displacement of the reference pixel array by one pixel in the horizontal direction, and ano is the pixel value of the pixel that is the horizontal origin of the reference pixel array after the reference pixel array has been displaced by one pixel to the right with respect to the previous position of the reference pixel array as a result of the last displacement of the reference pixel array by one pixel in the horizontal direction.
摘要翻译：一种基于RAM的搜索引擎，用于在运动估计搜索期间更新表示包含在参考像素阵列的水平行中的N个像素的值之和的水平和，在该运动估计搜索期间参考像素阵列在水平搜索中移位一个像素方向在运动估计搜索的多个迭代中的每一个期间。基于RAM的搜索引擎包括水平和修正器电路，其在参考像素阵列的任何位移之前累积参考像素阵列的水平行中包含的N个像素的值以产生水平和，并且更新水平通过使用以下等式计算新的水平和，求和：其中OSNEW是在水平方向上将参考像素阵列最后一次移位一个像素之后的新的水平和，OSOLD是参考像素的最后位移之前的水平和在水平方向上排列一个像素，a00是作为参考像素阵列在水平方向上最后一次移动一个像素之前的参考像素阵列的水平原点的像素的像素值，而ano是像素在参考像素阵列已经向ri移位一个像素之后，参考像素阵列的水平原点的像素的值作为参考像素阵列在水平方向上最后一次移位一个像素的结果，相对于参考像素阵列的先前位置的ght。

6. 发明授权

US5587629A Transformerless high-voltage generator circuit 失效
标题翻译：无变压器高压发生器电路
公开(公告)号：US5587629A
公开(公告)日：1996-12-24
申请号：US519907
申请日：1995-08-28
申请人： Viktor L. Gornstein
发明人： Viktor L. Gornstein
IPC分类号： H05B41/282 , H02M9/04 , H05B41/30 , H05B41/32 , H05B37/00
CPC分类号： H05B41/30
摘要： A transformerless high-voltage generator circuit includes an amplifier and a feedback circuit connected together to form an oscillator. Due to the configuration of the feedback circuit, a high-voltage output is obtained at an intermediate point within the feedback circuit without the use of a transformer. The resulting circuit may be used in various applications, such as an electronic photoflash unit, in order to reduce the size, weight and cost of the finished product by eliminating the need for a transformer to obtain the desired high voltage.
摘要翻译：无变压器高压发生器电路包括放大器和连接在一起以形成振荡器的反馈电路。由于反馈电路的配置，在不使用变压器的情况下，在反馈电路的中间点处获得高电压输出。所得到的电路可以用于各种应用中，例如电子闪光灯单元，以便通过消除对变压器获得期望的高电压的需要来减小成品的尺寸，重量和成本。

7. 发明授权

US5418573A Apparatus and method for producing periodic synchronization references forming a synchronization signal 失效
标题翻译：用于产生形成同步信号的周期性同步参考的装置和方法
公开(公告)号：US5418573A
公开(公告)日：1995-05-23
申请号：US95980
申请日：1993-07-22
申请人： Carlo Basile , Samuel O. Akiwumi-Assani , Viktor L. Gornstein
发明人： Carlo Basile , Samuel O. Akiwumi-Assani , Viktor L. Gornstein
IPC分类号： H04N5/06 , H03L7/00 , H04N5/12 , H04N7/56 , H04N21/43 , H04N5/04
CPC分类号： H04N21/4302 , H03L7/00 , H04N5/126 , H04N7/56
摘要： An apparatus, such as an adaptive flywheel, and method for producing periodic time references, forming a periodic time reference signal, from uncertain time references. A counter counts from a first count value to a second count value and provides a periodic time reference each time its count reaches the second count value. An error processing device, coupled to the counter, determines (a) whether an uncertain time reference is received within a predetermined range of count values (corresponding to a window of expectation), or (b) whether the absolute value of the average of an error, corresponding to the number of increment values before or after the second count value, whichever is lower, the count is at when an uncertain synchronization reference is received, and at least one previously determined error for at least one previously received uncertain synchronization reference is greater than WC/2 increment values. The error processing device causes the counter to reset the count to the first count value when, with respect to (a), an uncertain time reference is received when the count is at a count value other than one in the range of predetermined count values, and with respect to (b), the absolute value of the average error is greater than a predetermined number of (i.e., WC2) increment values.
摘要翻译：一种诸如自适应飞轮的装置，以及用于从不确定的时间基准产生周期性时间基准，形成周期时间参考信号的方法。计数器从第一计数值计数到第二计数值，并且每次其计数达到第二计数值时提供周期性时间参考。耦合到计数器的错误处理装置确定（a）在预定范围的计数值（对应于期望窗口）内是否接收到不确定的时间基准，或者（b）是否将平均值的绝对值错误，对应于在第二计数值之前或之后的增量值的数量（以较低者为准），计数在接收到不确定的同步参考时处于，并且至少一个先前确定的至少一个先前接收的不确定同步参考的误差为大于WC / 2增量值。误差处理装置使计数器将计数值复位为第一计数值，当（a）中，当计数值在预定计数值的范围内的计数值以外的计数值时，接收到不确定的时间基准，并且关于（b），平均误差的绝对值大于预定数量（即WC2）增量值。

8. 发明授权

US5657016A Variable length decoder with one of N length indicator 失效
标题翻译：可变长度解码器，其中一个N长度指示器
公开(公告)号：US5657016A
公开(公告)日：1997-08-12
申请号：US583149
申请日：1995-12-28
申请人： Michael Bakhmutsky , Viktor L. Gornstein , Howard B. Pein
发明人： Michael Bakhmutsky , Viktor L. Gornstein , Howard B. Pein
IPC分类号： H03M7/42 , H03M7/40
CPC分类号： H03M7/425
摘要： A high speed variable length decoder with an enhanced architecture for minimizing the propagation delays within the processing paths of the variable length decoder. The variable length decoder includes an input circuit for receiving code words and outputting a sequence of bits on a corresponding sequence of parallel lines that define a decoding window. The input circuit preferably includes a "one-hot" bit stream barrel shifter matrix having a shift input. The decoding window is input to a "one-hot" word length decoder that provides a numbered sequence of output lines. The "one-hot" word length output of the "one-hot" word length decoder is applied to an input of a "one-hot" ring barrel shifter matrix, and an input of a "one-hot" overflow barrel shifter matrix. The output of the "one-hot" ring barrel shifter matrix is a "one-hot" word pointer which shifts the decoding window to the next code word to be decoded. This enhanced "one-hot" architecture greatly accelerates the word length computation loop of the variable length decoder of the present invention relative to the presently available variable length decoders having a conventional architecture. The decoding window is also connected to the input of a code word value decoder circuit. The code word value decoder circuit determines the values of code words and provides the decoded values at the output of the variable length decoder. A control circuit controls the operation of the value decoding circuit, the word length computation loop, and the input circuit, in accordance with a prescribed decoding protocol, e.g., an MPEG protocol.
摘要翻译：一种具有增强架构的高速可变长度解码器，用于最小化可变长度解码器的处理路径内的传播延迟。可变长度解码器包括：输入电路，用于接收代码字，并在定义解码窗口的对应的并行线路序列上输出位序列。输入电路优选地包括具有移位输入的“一热”位流桶形移位器矩阵。解码窗口被输入到提供编号的输出行序列的“一个热”字长解码器。 “一热”字长解码器的“一热”字长输出被应用于“一热”桶桶形移位器矩阵的输入，并且输入“一热”溢出桶形移位器矩阵。 “一热”式桶形移位器矩阵的输出是将解码窗口移动到下一个要解码的代码字的“一热”字指针。这种增强的“一热”架构相对于具有传统架构的当前可用的可变长度解码器，极大地加速了本发明的可变长度解码器的字长计算环。解码窗口也连接到码字值解码器电路的输入端。码字值解码电路确定码字的值，并在可变长度解码器的输出端提供解码值。控制电路根据规定的解码协议（例如MPEG协议）控制值解码电路，字长计算环路和输入电路的操作。

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