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1. 发明授权

US07882472B2 Method, apparatus, and computer program product for automatically waiving non-compute indications for a timing analysis process 有权
标题翻译：方法，装置和计算机程序产品，用于自动放弃计时分析过程的非计算指示
公开(公告)号：US07882472B2
公开(公告)日：2011-02-01
申请号：US11871179
申请日：2007-10-12
申请人： Nicholas P. Sardino , Sean M. Carey , Christopher M. Carney , Vern Anthony Victoria
发明人： Nicholas P. Sardino , Sean M. Carey , Christopher M. Carney , Vern Anthony Victoria
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： In the course of unit timing, there exists the possibility for a non-compute (N/C) on a particular net in an IC chip design, which could be caused by numerous things, including but not limited to a pin being tied to power, a floating output, or invalid timing test for a given phase at a test point. A process automatically verifies that all non-computes are understood and exist for valid reasons, in order to ensure all necessary paths are being timed. The process takes a conventional Comprehensive Report output of a unit timing run and generates macro specific N/C reports for designers to review and sign off on.
摘要翻译：在单元定时过程中，存在在IC芯片设计中的特定网络上的非计算（N / C）的可能性，其可能由许多事情引起，包括但不限于引脚被绑定到电源，浮动输出或在测试点的给定阶段的无效时序测试。过程会自动验证所有非计算机是否被理解并存在，以确保所有必需的路径都被计时。该过程采用单位计时运行的常规综合报告输出，并为设计人员生成宏观特定的N / C报告进行审查和签名。

2. 发明申请

US20090100394A1 Method, Apparatus, and Computer Program Product for Automatically Waiving Non-Compute Indications for a Timing Analysis Process 有权
标题翻译：方法，设备和计算机程序产品，用于自动放弃用于定时分析过程的非计算指示
公开(公告)号：US20090100394A1
公开(公告)日：2009-04-16
申请号：US11871179
申请日：2007-10-12
申请人： Nicholas P. Sardino , Sean M. Carey , Christopher M. Carney , Vern Anthony Victoria
发明人： Nicholas P. Sardino , Sean M. Carey , Christopher M. Carney , Vern Anthony Victoria
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： In the course of unit timing, there exists the possibility for a non-compute (N/C) on a particular net in an IC chip design, which could be caused by numerous things, including but not limited to a pin being tied to power, a floating output, or invalid timing test for a given phase at a test point. A process automatically verifies that all non-computes are understood and exist for valid reasons, in order to ensure all necessary paths are being timed. The process takes a conventional Comprehensive Report output of a unit timing run and generates macro specific N/C reports for designers to review and sign off on.
摘要翻译：在单元定时过程中，存在在IC芯片设计中的特定网络上的非计算（N / C）的可能性，其可能由许多事情引起，包括但不限于引脚被绑定到电源，浮动输出或在测试点的给定阶段的无效时序测试。过程会自动验证所有非计算机是否被理解并存在，以确保所有必需的路径都被计时。该过程采用单位计时运行的常规综合报告输出，并为设计人员生成宏观特定的N / C报告进行审查和签名。

3. 发明授权

US08185371B2 Modeling full and half cycle clock variability 失效
标题翻译：建模全半周期时钟变化
公开(公告)号：US08185371B2
公开(公告)日：2012-05-22
申请号：US12424400
申请日：2009-04-15
申请人： Adil Bhanji , Sean Michael Carey , Jack Dilullo , Prashant D Joshi , Don Richard Rozales , Vern Anthony Victoria , Albert Thomas Williams
发明人： Adil Bhanji , Sean Michael Carey , Jack Dilullo , Prashant D Joshi , Don Richard Rozales , Vern Anthony Victoria , Albert Thomas Williams
IPC分类号： G06F17/50 , G06F9/44 , G06F13/10 , G06F13/12 , G06F1/00 , G06F9/455
CPC分类号： G06F17/5031
摘要： A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.
摘要翻译：建模系统包括具有在设计模型上执行静态时序分析（STA）的软件的处理器。 STA软件执行以缩短的时钟周期运行的静态时序分析（STA）来建模全周期时钟变化。设计人员或其他实体通过对输出数据进行建模来解释缩短的STA运行数据的结果，以产生设计模型数据路径的松弛数据。 STA软件执行具有扩展时钟周期的STA运行，以便从全周期数据路径（FCDP）松弛数据自动分离半周期数据路径（HCDP）松弛数据。全周期和半周期时钟可变性方法可以自动调整所有半周期数据路径（HCDP）的松弛数据，以考虑额外的半周期变化（AHCV）和半周期时钟边沿变化，这可能会对设计模型造成影响硬件实现。

4. 发明申请

US20100268522A1 MODELING FULL AND HALF CYCLE CLOCK VARIABILITY 失效
标题翻译：建模充分和半周期时钟变化
公开(公告)号：US20100268522A1
公开(公告)日：2010-10-21
申请号：US12424400
申请日：2009-04-15
申请人： Adil Bhanji , Sean Michael Carey , Jack Dilullo , Prashant D Joshi , Don Richard Rozales , Vern Anthony Victoria , Albert Thomas Williams
发明人： Adil Bhanji , Sean Michael Carey , Jack Dilullo , Prashant D Joshi , Don Richard Rozales , Vern Anthony Victoria , Albert Thomas Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation. Designers use a sort of slack data for half cycle data paths (HCDP)s independent of the slack data for the full cycle data path (FCDP)s to modify or otherwise perform design changes to the design model prior to hardware implementation.
摘要翻译：建模系统包括具有在设计模型上执行静态时序分析（STA）的软件的处理器。 STA软件执行以缩短的时钟周期运行的静态时序分析（STA）来建模全周期时钟变化。设计人员或其他实体通过对输出数据进行建模来解释缩短的STA运行数据的结果，以产生设计模型数据路径的松弛数据。 STA软件执行具有扩展时钟周期的STA运行，以便从全周期数据路径（FCDP）松弛数据自动分离半周期数据路径（HCDP）松弛数据。全周期和半周期时钟可变性方法可以自动调整所有半周期数据路径（HCDP）的松弛数据，以考虑额外的半周期变化（AHCV）和半周期时钟边沿变化，这可能会对设计模型造成影响硬件实现。设计师使用一种与半周期数据路径（HCDP）无关的松弛数据，独立于全周期数据路径（FCDP）的松弛数据，以在硬件实现之前修改或执行设计模型的设计更改。

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