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1. 发明授权

US08897086B2 Method and apparatus for memory fault tolerance 有权
标题翻译：存储器容错的方法和装置
公开(公告)号：US08897086B2
公开(公告)日：2014-11-25
申请号：US13758211
申请日：2013-02-04
申请人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
发明人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
IPC分类号： G11C29/04 , G11C7/10 , G11C29/00 , G11C29/44
CPC分类号： G11C29/00 , G06F11/1048 , G11C7/1006 , G11C29/04 , G11C29/76 , G11C29/785 , G11C2029/0409 , G11C2029/4402
摘要： One or more circuits may comprise an array of memory cells corresponding to a particular memory address, and a memory fault mitigation module. The one or more circuits may be operable to write a data block to the array of memory cells. The write operation may comprises a swap of a first portion of the data block with a second portion of the data block in response to a detection that one or more memory cells of the array is faulty, and storing the data block to the array of memory cells after the swap.
摘要翻译：一个或多个电路可以包括对应于特定存储器地址的存储器单元阵列和存储器故障缓解模块。一个或多个电路可以用于将数据块写入存储器单元阵列。响应于阵列的一个或多个存储单元故障的检测，写入操作可以包括数据块的第一部分与数据块的第二部分的交换，并将数据块存储到存储器阵列互换后的细胞。

2. 发明申请

US20130141995A1 METHOD AND APPARATUS FOR MEMORY FAULT TOLERANCE 有权
标题翻译：用于记忆容忍度的方法和装置
公开(公告)号：US20130141995A1
公开(公告)日：2013-06-06
申请号：US13758187
申请日：2013-02-04
申请人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
发明人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
IPC分类号： G11C29/00
CPC分类号： G11C29/00 , G06F11/1048 , G11C7/1006 , G11C29/04 , G11C29/76 , G11C29/785 , G11C2029/0409 , G11C2029/4402
摘要： One or more circuits may include an array of memory cells corresponding to a particular memory address. The one or more circuits may be operable to discover a location of a faulty memory cell in the array of memory cells. The one or more circuits may be operable to arrange the order in which the bits of a data block are stored to said array of memory cells based, at least in part, on said discovered location of said faulty memory cell.
摘要翻译：一个或多个电路可以包括对应于特定存储器地址的存储器单元的阵列。一个或多个电路可以用于发现存储器单元阵列中的故障存储器单元的位置。所述一个或多个电路可以用于至少部分地基于所述故障存储器单元的所述发现位置来将数据块的位存储到所述存储器单元阵列的顺序。

3. 发明授权

US08797813B2 Method and apparatus for memory power and/or area reduction 有权
标题翻译：用于存储器功率和/或面积减小的方法和装置
公开(公告)号：US08797813B2
公开(公告)日：2014-08-05
申请号：US13285945
申请日：2011-10-31
申请人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
发明人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
IPC分类号： G11C29/00 , G11C29/02 , G11C29/04
CPC分类号： G11C5/144 , G06F11/1048 , G11C5/14 , G11C29/021 , G11C29/028 , G11C2029/0409
摘要： A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.
摘要翻译：一种用于存储器功率和/或面积减小的方法和装置。可以扫描存储器单元阵列以检测阵列中的故障存储器单元（如果有的话）。可以基于扫描的结果并且基于存储器单元阵列中的一个或多个的灵敏度系数来控制施加到存储器单元阵列的电源电压Vmem。灵敏度系数可以指示存储器单元阵列中的一个或多个存在故障的影响可能对于将数据读取和写入存储器阵列的设备的性能有影响。附加地或替代地，存储器单元的物理尺寸可以基于灵敏度系数和/或基于可以在存储器单元阵列中容忍的故障存储器单元的数量来确定。

4. 发明授权

US08705298B2 Method and apparatus for memory fault tolerance 有权
标题翻译：存储器容错的方法和装置
公开(公告)号：US08705298B2
公开(公告)日：2014-04-22
申请号：US13758187
申请日：2013-02-04
申请人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
发明人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
IPC分类号： G11C29/00
CPC分类号： G11C29/00 , G06F11/1048 , G11C7/1006 , G11C29/04 , G11C29/76 , G11C29/785 , G11C2029/0409 , G11C2029/4402
摘要： One or more circuits may include an array of memory cells corresponding to a particular memory address. The one or more circuits may be operable to discover a location of a faulty memory cell in the array of memory cells. The one or more circuits may be operable to arrange the order in which the bits of a data block are stored to said array of memory cells based, at least in part, on said discovered location of said faulty memory cell.
摘要翻译：一个或多个电路可以包括对应于特定存储器地址的存储器单元的阵列。一个或多个电路可以用于发现存储器单元阵列中的故障存储器单元的位置。至少部分地基于所述故障存储器单元的所述发现位置，所述一个或多个电路可以用于将数据块的位存储到所述存储器单元阵列的顺序。

5. 发明申请

US20130141996A1 METHOD AND APPARATUS FOR MEMORY FAULT TOLERANCE 有权
标题翻译：用于记忆容忍度的方法和装置
公开(公告)号：US20130141996A1
公开(公告)日：2013-06-06
申请号：US13758211
申请日：2013-02-04
申请人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
发明人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
IPC分类号： G11C29/04
CPC分类号： G11C29/00 , G06F11/1048 , G11C7/1006 , G11C29/04 , G11C29/76 , G11C29/785 , G11C2029/0409 , G11C2029/4402
摘要： One or more circuits may comprise an array of memory cells corresponding to a particular memory address, and a memory fault mitigation module. The one or more circuits may be operable to write a data block to the array of memory cells. The write operation may comprises a swap of a first portion of the data block with a second portion of the data block in response to a detection that one or more memory cells of the array is faulty, and storing the data block to the array of memory cells after the swap.
摘要翻译：一个或多个电路可以包括对应于特定存储器地址的存储器单元阵列和存储器故障缓解模块。一个或多个电路可以用于将数据块写入存储器单元阵列。响应于阵列的一个或多个存储单元故障的检测，写入操作可以包括数据块的第一部分与数据块的第二部分的交换，并将数据块存储到存储器阵列互换后的细胞。

6. 发明申请

US20120294100A1 METHOD AND APPARATUS FOR MEMORY POWER AND/OR AREA REDUCTION 有权
标题翻译：用于存储功率和/或区域减少的方法和装置
公开(公告)号：US20120294100A1
公开(公告)日：2012-11-22
申请号：US13285945
申请日：2011-10-31
申请人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
发明人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
IPC分类号： G11C29/00
CPC分类号： G11C5/144 , G06F11/1048 , G11C5/14 , G11C29/021 , G11C29/028 , G11C2029/0409
摘要： A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.
摘要翻译：一种用于存储器功率和/或面积减小的方法和装置。可以扫描存储器单元阵列以检测阵列中的故障存储器单元（如果有的话）。可以基于扫描的结果并且基于存储器单元阵列中的一个或多个的灵敏度系数来控制施加到存储器单元阵列的电源电压Vmem。灵敏度系数可以指示存储器单元阵列中的一个或多个存在故障的影响可能对于将数据读取和写入存储器阵列的设备的性能有影响。附加地或替代地，存储器单元的物理尺寸可以基于灵敏度系数和/或基于可以在存储器单元阵列中容忍的故障存储器单元的数量来确定。

7. 发明申请

US20120294094A1 METHOD AND APPARATUS FOR MEMORY FAULT TOLERANCE 有权
标题翻译：用于记忆容忍度的方法和装置
公开(公告)号：US20120294094A1
公开(公告)日：2012-11-22
申请号：US13285864
申请日：2011-10-31
申请人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
发明人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
IPC分类号： G11C7/10 , G11C7/00 , G11C29/00
CPC分类号： G11C29/00 , G06F11/1048 , G11C7/1006 , G11C29/04 , G11C29/76 , G11C29/785 , G11C2029/0409 , G11C2029/4402
摘要： A plurality of data lines and a plurality of bit lines may be used to write to and/or read from an array of memory cells. A switching element may select among different mappings between the plurality of data lines and the plurality of bit lines. The array may, for example, consist of N memory cells, the plurality of bit lines may consist of N bit lines, and the plurality of data lines may consist of N data lines, where N is an integer greater than 1. For a write operation in which a data block is to be written to the array, a configuration of the switching element may be controlled based, at least in part, on how sensitive the data block is to a faulty memory cell among the array of memory cells.
摘要翻译：可以使用多条数据线和多条位线来写入和/或从存储器单元阵列读取。开关元件可以在多条数据线与多条位线之间的不同映射中进行选择。阵列可以例如由N个存储器单元组成，多个位线可以由N个位线组成，并且多个数据线可以由N个数据线组成，其中N是大于1的整数。对于写入至少部分地基于数据块对存储器单元阵列中的故障存储器单元的敏感度来控制开关元件的配置，其中将数据块写入阵列的操作。

8. 发明授权

US09165677B2 Method and apparatus for memory fault tolerance 有权
标题翻译：存储器容错的方法和装置
公开(公告)号：US09165677B2
公开(公告)日：2015-10-20
申请号：US13285864
申请日：2011-10-31
申请人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
发明人： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
IPC分类号： G11C7/10 , G11C7/00 , G11C29/08 , G11C29/00 , G06F11/10 , G11C29/04 , G11C29/44
CPC分类号： G11C29/00 , G06F11/1048 , G11C7/1006 , G11C29/04 , G11C29/76 , G11C29/785 , G11C2029/0409 , G11C2029/4402
摘要： A plurality of data lines and a plurality of bit lines may be used to write to and/or read from an array of memory cells. A switching element may select among different mappings between the plurality of data lines and the plurality of bit lines. The array may, for example, consist of N memory cells, the plurality of bit lines may consist of N bit lines, and the plurality of data lines may consist of N data lines, where N is an integer greater than 1. For a write operation in which a data block is to be written to the array, a configuration of the switching element may be controlled based, at least in part, on how sensitive the data block is to a faulty memory cell among the array of memory cells.
摘要翻译：可以使用多条数据线和多条位线来写入和/或从存储器单元阵列读取。开关元件可以在多条数据线与多条位线之间的不同映射中进行选择。阵列可以例如由N个存储器单元组成，多个位线可以由N个位线组成，并且多个数据线可以由N个数据线组成，其中N是大于1的整数。对于写入至少部分地基于数据块对存储器单元阵列中的故障存储器单元的敏感度来控制开关元件的配置，其中将数据块写入阵列的操作。

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