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1. 发明申请

US20140001564A1 SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF DESIGNING THE SAME, AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体集成电路，其设计方法及其制造方法
公开(公告)号：US20140001564A1
公开(公告)日：2014-01-02
申请号：US13800483
申请日：2013-03-13
申请人： Tae-joong SONG , Pil-un KO , Gyu-hong KIM , Jong-hoon JUNG
发明人： Tae-joong SONG , Pil-un KO , Gyu-hong KIM , Jong-hoon JUNG
IPC分类号： G06F17/50 , H01L27/092
CPC分类号： G06F17/5072 , G06F17/50 , G06F17/5077 , G06F17/5081 , H01L27/0207 , H01L27/092 , H01L27/0924 , H01L29/6681
摘要： A semiconductor integrated circuit designing method capable of minimizing a parasitic capacitance generated by an overhead in conductive lines, especially a gate line, a semiconductor integrated circuit according to the designing method, and a fabricating method thereof are provided. A method of designing a semiconductor integrated circuit having a FinFET architecture, includes: performing a pre-simulation of the semiconductor integrated circuit to be designed; designing a layout of components of the semiconductor integrated circuit based on a result of the pre-simulation, the components comprising first and second device areas and a first conductive line extending across the first and second device areas; modifying a first cutting area, that is arranged between the first and second device areas and electrically cuts the first conductive line, according to at least one design rule to minimize an overhead of the first conductive line created by the first cutting area.
摘要翻译：提供了一种半导体集成电路设计方法及其制造方法，该方法能够最小化由导线，特别是栅极线，半导体集成电路中的开销产生的寄生电容及其制造方法。一种设计具有FinFET架构的半导体集成电路的方法，包括：对要设计的半导体集成电路进行预仿真; 基于预仿真的结果设计半导体集成电路的部件的布局，所述部件包括第一和第二器件区域以及跨越第一和第二器件区域延伸的第一导电线; 根据至少一个设计规则修改布置在第一和第二设备区域之间并且电切割第一导电线的第一切割区域，以使由第一切割区域产生的第一导电线路的开销最小化。

2. 发明申请

US20130102740A1 SULFONATED POLY(ARYLENE ETHER) COPOLYMER HAVING A CROSS-LINKABLE STRUCTURE, AND POLYELECTROLYTE MEMBRANE COMPRISING SAME 审中-公开
标题翻译：具有交联结构的磺化聚（亚乙基醚）共聚物和包含其的聚电解质膜
公开(公告)号：US20130102740A1
公开(公告)日：2013-04-25
申请号：US13807455
申请日：2011-07-13
申请人： Jae-Suk Lee , Young Jea Kim , Hyo Kyeong Son , Da Young Kim , Un Ko
发明人： Jae-Suk Lee , Young Jea Kim , Hyo Kyeong Son , Da Young Kim , Un Ko
IPC分类号： C08G75/23 , C08G65/40
CPC分类号： C08G75/23 , C08G65/40 , C08G65/4006 , C08G65/48 , H01M8/1025 , H01M8/1027 , H01M8/1032 , H01M8/1037 , H01M8/1039 , H01M8/1072 , H01M8/1081 , H01M2008/1095 , H01M2300/0082 , Y02P70/56
摘要： Provided are a sulfonated poly(arylene ether) copolymer including a crosslinking structure and a polyelectrolyte membrane including the same. Particularly, a sulfonated poly(arylene ether) copolymer including a crosslinking structure in a polymer chain or at the terminal portion of the polymer chain, and a polyelectrolyte membrane including the same are provided. The polyelectrolyte membrane using the sulfonated poly(arylene ether) copolymer including the crosslinking structure, may have the same or better degree of a thermal stability, a mechanical stability, a chemical stability, a membrane forming capability, etc. than a commonly used polyelectrolyte membrane. In addition, the proton conductivity and the cell performance of the polyelectrolyte membrane may be remarkably improved than those of the commonly used polymer electrolyte. Further, the properties of the electrolyte membrane may be rarely changed, and a high measuring stability may be obtainable. The polyelectrolyte membrane may be used in a fuel cell or a secondary battery.
摘要翻译：提供包含交联结构的磺化聚（亚芳基醚）共聚物和包含其的聚电解质膜。特别地，提供了在聚合物链或聚合物链的末端部分包含交联结构的磺化聚（亚芳基醚）共聚物和包含该聚合物的聚电解质膜。使用包含交联结构的磺化聚（亚芳基醚）共聚物的聚电解质膜可以具有与常用的聚电解质膜相同或更好的热稳定性，机械稳定性，化学稳定性，成膜能力等。。此外，与常用聚合物电解质相比，聚电解质膜的质子传导性和电池性能可显着提高。此外，电解质膜的性质可能很少改变，并且可以获得高的测量稳定性。聚电解质膜可以用于燃料电池或二次电池。

3. 发明授权

US09026975B2 Semiconductor integrated circuit, method of designing the same, and method of fabricating the same 有权
标题翻译：半导体集成电路及其设计方法及其制造方法
公开(公告)号：US09026975B2
公开(公告)日：2015-05-05
申请号：US13800483
申请日：2013-03-13
申请人： Tae-joong Song , Pil-un Ko , Gyu-hong Kim , Jong-hoon Jung
发明人： Tae-joong Song , Pil-un Ko , Gyu-hong Kim , Jong-hoon Jung
IPC分类号： G06F17/50 , H01L27/092 , H01L27/02
CPC分类号： G06F17/5072 , G06F17/50 , G06F17/5077 , G06F17/5081 , H01L27/0207 , H01L27/092 , H01L27/0924 , H01L29/6681
摘要： A semiconductor integrated circuit designing method capable of minimizing a parasitic capacitance generated by an overhead in conductive lines, especially a gate line, a semiconductor integrated circuit according to the designing method, and a fabricating method thereof are provided. A method of designing a semiconductor integrated circuit having a FinFET architecture, includes: performing a pre-simulation of the semiconductor integrated circuit to be designed; designing a layout of components of the semiconductor integrated circuit based on a result of the pre-simulation, the components comprising first and second device areas and a first conductive line extending across the first and second device areas; modifying a first cutting area, that is arranged between the first and second device areas and electrically cuts the first conductive line, according to at least one design rule to minimize an overhead of the first conductive line created by the first cutting area.
摘要翻译：提供了一种半导体集成电路设计方法及其制造方法，该方法能够最小化由导线，特别是栅极线，半导体集成电路中的开销产生的寄生电容及其制造方法。一种设计具有FinFET架构的半导体集成电路的方法，包括：对要设计的半导体集成电路进行预仿真; 基于预仿真的结果设计半导体集成电路的部件的布局，所述部件包括第一和第二器件区域以及跨越第一和第二器件区域延伸的第一导电线; 根据至少一个设计规则修改布置在第一和第二设备区域之间并且电切割第一导电线的第一切割区域，以使由第一切割区域产生的第一导电线路的开销最小化。

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