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1. 发明申请

US20120133049A1 Process of Fabricating Semiconductor Device and Through Substrate via, and Through Substrate via Structure Therefrom 有权
标题翻译：制造半导体器件和通过衬底通过衬底通过结构的工艺
公开(公告)号：US20120133049A1
公开(公告)日：2012-05-31
申请号：US13303208
申请日：2011-11-23
申请人： Chia-Sheng Lin , Chien-Hui Chen , Bing-Siang Chen , Tzu-Hsiang Hung
发明人： Chia-Sheng Lin , Chien-Hui Chen , Bing-Siang Chen , Tzu-Hsiang Hung
IPC分类号： H01L23/538 , H01L21/50 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device, a process of fabricating a through substrate via and a substrate with through vias are provided. The substrate with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers.
摘要翻译：提供了制造半导体器件的方法，制造通孔基板通孔的工艺和具有通孔的基板。具有贯通孔的基板包括具有后表面和穿过背面的通孔的半导体基板，金属层，第一绝缘层和第二绝缘层。第一绝缘层形成在基板的背面，并且具有连接到通孔的开口。第二绝缘层形成在第一绝缘层上，并且具有延伸到开口中的部分和通孔以形成沟槽绝缘层。沟槽绝缘层的底部被回蚀以在通孔的拐角处形成基部。所述基脚部分的高度小于所述第一和第二绝缘层的总高度。

2. 发明申请

US20120193786A1 CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
标题翻译：芯片包装及其形成方法
公开(公告)号：US20120193786A1
公开(公告)日：2012-08-02
申请号：US13359452
申请日：2012-01-26
申请人： Chia-Sheng LIN , Tzu-Hsiang HUNG
发明人： Chia-Sheng LIN , Tzu-Hsiang HUNG
IPC分类号： H01L23/498 , H01L21/50
CPC分类号： H01L21/76898 , H01L23/3157 , H01L23/481 , H01L23/522 , H01L23/60 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02372 , H01L2224/02375 , H01L2224/02377 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/13022 , H01L2224/13024 , H01L2924/00014 , H01L2924/12041 , H01L2924/1461 , H01L2924/15787 , H01L2924/15788 , H01L2924/00 , H01L2224/05552
摘要： An embodiment of the invention provides a chip package which includes: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; and a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers the entire side terminals of the signal conducting layer and partially covers the ground conducting layer such that a side terminal of the ground conducting layer is exposed on a side of the substrate.
摘要翻译：本发明的实施例提供了一种芯片封装，其包括：衬底; 设置在所述基板中或所述基板上的器件区域; 信号焊盘，设置在所述衬底中或所述衬底上并电连接到所述器件区域; 设置在基板中或基板上的接地焊盘; 设置在所述基板的表面上的信号凸起，其中所述信号凸起通过信号传导层电连接到所述信号焊盘; 接地导电层，设置在所述基板的表面上并电连接到所述接地垫; 以及设置在基板的表面上的保护层，其中保护层完全覆盖信号传导层的整个侧面端子并且部分地覆盖接地导电层，使得接地导电层的侧端子暴露在底物。

3. 发明申请

US20120056226A1 CHIP PACKAGE 有权
标题翻译：芯片包装
公开(公告)号：US20120056226A1
公开(公告)日：2012-03-08
申请号：US13224267
申请日：2011-09-01
申请人： Tzu-Hsiang HUNG , Hsin-Chih CHIU , Chuan-Jin SHIU , Chia-Sheng LIN , Yen-Shih HO , Yu-Min LIANG
发明人： Tzu-Hsiang HUNG , Hsin-Chih CHIU , Chuan-Jin SHIU , Chia-Sheng LIN , Yen-Shih HO , Yu-Min LIANG
IPC分类号： H01L33/58 , H01L31/0232
CPC分类号： H01L27/14618 , H01L2224/13 , H01L2224/13022 , H01L2224/131 , H01L2924/13091 , H01L2924/1461 , H01L2933/0066 , H01L2924/014 , H01L2924/00
摘要： An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer disposed on the second surface of the substrate, wherein the protection layer has an opening; a conducting bump disposed on the second surface of the substrate and filled in the opening; a conducting layer disposed between the protection layer and the substrate, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump; and a light shielding layer disposed on the protection layer, wherein the light shielding layer does not contact with the conducting bump.
摘要翻译：本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 设置在第一表面处的光电子器件; 保护层，设置在所述基板的第二表面上，其中所述保护层具有开口; 设置在所述基板的第二表面上并填充在所述开口中的导电凸块; 设置在所述保护层和所述基板之间的导电层，其中所述导电层将所述光电子器件电连接到所述导电凸块; 以及设置在保护层上的遮光层，其中遮光层不与导电凸块接触。

4. 发明申请

US20120049307A1 IMAGE SENSOR CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
标题翻译：图像传感器芯片封装及其形成方法
公开(公告)号：US20120049307A1
公开(公告)日：2012-03-01
申请号：US13217999
申请日：2011-08-25
申请人： Yu-Lung HUANG , Tzu-Hsiang HUNG , Yen-Shih HO
发明人： Yu-Lung HUANG , Tzu-Hsiang HUNG , Yen-Shih HO
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H01L31/1876 , H01L27/14618 , H01L27/14687 , H01L2224/13 , H01L2224/94
摘要： A method for forming an image sensor chip package includes: providing a substrate having predetermined scribe lines defined thereon, wherein the predetermined scribe lines define device regions and each of the device regions has at least a device formed therein; disposing a support substrate on a first surface of the substrate; forming at least a spacer layer between the support substrate and the substrate, wherein the spacer layer covers the predetermined scribe lines; forming a package layer on a second surface of the substrate; forming conducting structures on the second surface of the substrate, wherein the conducting structures are electrically connected to the corresponding device in corresponding one of the device regions, respectively; and dicing along the predetermined scribe lines such that the support substrate is removed from the substrate and the substrate is separated into a plurality of individual image sensor chip packages.
摘要翻译：一种用于形成图像传感器芯片封装的方法，包括：提供具有限定在其上的预定划线的基板，其中，所述预定划线限定器件区域，并且每个器件区域至少具有形成在其中的器件; 将支撑基板设置在所述基板的第一表面上; 在所述支撑基板和所述基板之间形成至少间隔层，其中所述间隔层覆盖所述预定划线; 在所述基板的第二表面上形成封装层; 在所述衬底的第二表面上形成导电结构，其中所述导电结构分别在相应的一个所述器件区域中电连接到相应的器件; 并且沿着预定的划线切割，使得支撑基板从基板移除，并且基板被分离成多个单独的图像传感器芯片封装。

5. 发明授权

US08878367B2 Substrate structure with through vias 有权
标题翻译：基板结构与通孔
公开(公告)号：US08878367B2
公开(公告)日：2014-11-04
申请号：US13303208
申请日：2011-11-23
申请人： Chia-Sheng Lin , Chien-Hui Chen , Bing-Siang Chen , Tzu-Hsiang Hung
发明人： Chia-Sheng Lin , Chien-Hui Chen , Bing-Siang Chen , Tzu-Hsiang Hung
IPC分类号： H01L23/538 , H01L21/50 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76898 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A substrate structure with through vias is provided. The substrate structure with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the semiconductor substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers.
摘要翻译：提供具有通孔的衬底结构。具有贯通孔的衬底结构包括具有后表面和穿过背面的通孔的半导体衬底，金属层，第一绝缘层和第二绝缘层。第一绝缘层形成在半导体衬底的后表面上，并且具有连接到通孔的开口。第二绝缘层形成在第一绝缘层上，并且具有延伸到开口中的部分和通孔以形成沟槽绝缘层。沟槽绝缘层的底部被回蚀以在通孔的拐角处形成基部。所述基脚部分的高度小于所述第一和第二绝缘层的总高度。

6. 发明授权

US08779452B2 Chip package 有权
标题翻译：芯片封装
公开(公告)号：US08779452B2
公开(公告)日：2014-07-15
申请号：US13224267
申请日：2011-09-01
申请人： Tzu-Hsiang Hung , Hsin-Chih Chiu , Chuan-Jin Shiu , Chia-Sheng Lin , Yen-Shih Ho , Yu-Min Liang
发明人： Tzu-Hsiang Hung , Hsin-Chih Chiu , Chuan-Jin Shiu , Chia-Sheng Lin , Yen-Shih Ho , Yu-Min Liang
IPC分类号： H01L29/22
CPC分类号： H01L27/14618 , H01L2224/13 , H01L2224/13022 , H01L2224/131 , H01L2924/13091 , H01L2924/1461 , H01L2933/0066 , H01L2924/014 , H01L2924/00
摘要： An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer disposed on the second surface of the substrate, wherein the protection layer has an opening; a conducting bump disposed on the second surface of the substrate and filled in the opening; a conducting layer disposed between the protection layer and the substrate, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump; and a light shielding layer disposed on the protection layer, wherein the light shielding layer does not contact with the conducting bump.
摘要翻译：本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 设置在第一表面处的光电子器件; 保护层，设置在所述基板的第二表面上，其中所述保护层具有开口; 设置在所述基板的第二表面上并填充在所述开口中的导电凸块; 设置在所述保护层和所述基板之间的导电层，其中所述导电层将所述光电子器件电连接到所述导电凸块; 以及设置在保护层上的遮光层，其中遮光层不与导电凸块接触。

7. 发明授权

US08786093B2 Chip package and method for forming the same 有权
标题翻译：芯片封装及其形成方法
公开(公告)号：US08786093B2
公开(公告)日：2014-07-22
申请号：US13359452
申请日：2012-01-26
申请人： Chia-Sheng Lin , Tzu-Hsiang Hung
发明人： Chia-Sheng Lin , Tzu-Hsiang Hung
IPC分类号： H01L23/48 , H01L21/44 , H01L23/60 , H01L23/522 , H01L23/31 , H01L23/00 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/3157 , H01L23/481 , H01L23/522 , H01L23/60 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02372 , H01L2224/02375 , H01L2224/02377 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/13022 , H01L2224/13024 , H01L2924/00014 , H01L2924/12041 , H01L2924/1461 , H01L2924/15787 , H01L2924/15788 , H01L2924/00 , H01L2224/05552
摘要： An embodiment of the invention provides a chip package which includes: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; and a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers the entire side terminals of the signal conducting layer and partially covers the ground conducting layer such that a side terminal of the ground conducting layer is exposed on a side of the substrate.
摘要翻译：本发明的实施例提供了一种芯片封装，其包括：衬底; 设置在所述基板中或所述基板上的器件区域; 信号焊盘，设置在所述衬底中或所述衬底上并电连接到所述器件区域; 设置在基板中或基板上的接地焊盘; 设置在所述基板的表面上的信号凸起，其中所述信号凸起通过信号传导层电连接到所述信号焊盘; 接地导电层，设置在所述基板的表面上并电连接到所述接地垫; 以及设置在基板的表面上的保护层，其中保护层完全覆盖信号传导层的整个侧面端子并且部分地覆盖接地导电层，使得接地导电层的侧端子暴露在底物。

8. 发明授权

US08742564B2 Chip package and method for forming the same 有权
标题翻译：芯片封装及其形成方法
公开(公告)号：US08742564B2
公开(公告)日：2014-06-03
申请号：US13350520
申请日：2012-01-13
申请人： Bai-Yao Lou , Tsang-Yu Liu , Chia-Sheng Lin , Tzu-Hsiang Hung
发明人： Bai-Yao Lou , Tsang-Yu Liu , Chia-Sheng Lin , Tzu-Hsiang Hung
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/04 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/32 , H01L24/73 , H01L2224/02371 , H01L2224/02372 , H01L2224/0392 , H01L2224/0401 , H01L2224/04026 , H01L2224/05025 , H01L2224/05548 , H01L2224/05572 , H01L2224/056 , H01L2224/05687 , H01L2224/0569 , H01L2224/06181 , H01L2224/13022 , H01L2224/13024 , H01L2224/32225 , H01L2224/73153 , H01L2924/00013 , H01L2924/00014 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2924/00012 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要： An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening.
摘要翻译：本发明的实施例提供一种芯片封装，其包括具有第一表面和第二表面的基板; 位于所述第一表面上的导电垫结构; 位于所述基板的所述第一表面上的电介质层和所述导电焊盘结构，其中所述电介质层具有暴露所述导电焊盘结构的一部分的开口; 以及位于电介质层上并填充到开口中的盖层。

9. 发明授权

US08692358B2 Image sensor chip package and method for forming the same 有权
标题翻译：图像传感器芯片封装及其形成方法
公开(公告)号：US08692358B2
公开(公告)日：2014-04-08
申请号：US13217999
申请日：2011-08-25
申请人： Yu-Lung Huang , Tzu-Hsiang Hung , Yen-Shih Ho
发明人： Yu-Lung Huang , Tzu-Hsiang Hung , Yen-Shih Ho
IPC分类号： H01L29/40 , H01L23/52 , H01L23/48 , H01L31/0232 , H01L29/22 , H01L23/538
CPC分类号： H01L31/1876 , H01L27/14618 , H01L27/14687 , H01L2224/13 , H01L2224/94
摘要： A method for forming an image sensor chip package includes: providing a substrate having predetermined scribe lines defined thereon, wherein the predetermined scribe lines define device regions and each of the device regions has at least a device formed therein; disposing a support substrate on a first surface of the substrate; forming at least a spacer layer between the support substrate and the substrate, wherein the spacer layer covers the predetermined scribe lines; forming a package layer on a second surface of the substrate; forming conducting structures on the second surface of the substrate, wherein the conducting structures are electrically connected to the corresponding device in corresponding one of the device regions, respectively; and dicing along the predetermined scribe lines such that the support substrate is removed from the substrate and the substrate is separated into a plurality of individual image sensor chip packages.
摘要翻译：一种用于形成图像传感器芯片封装的方法，包括：提供具有限定在其上的预定划线的基板，其中，所述预定划线限定器件区域，并且每个器件区域至少具有形成在其中的器件; 将支撑基板设置在所述基板的第一表面上; 在所述支撑基板和所述基板之间形成至少间隔层，其中所述间隔层覆盖所述预定划线; 在所述基板的第二表面上形成封装层; 在所述衬底的第二表面上形成导电结构，其中所述导电结构分别在相应的一个所述器件区域中电连接到相应的器件; 并且沿着预定的划线切割，使得支撑基板从基板移除，并且基板被分离成多个单独的图像传感器芯片封装。

10. 发明申请

US20120181672A1 CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
标题翻译：芯片包装及其形成方法
公开(公告)号：US20120181672A1
公开(公告)日：2012-07-19
申请号：US13350520
申请日：2012-01-13
申请人： Bai-Yao LOU , Tsang-Yu LIU , Chia-Sheng LIN , Tzu-Hsiang HUNG
发明人： Bai-Yao LOU , Tsang-Yu LIU , Chia-Sheng LIN , Tzu-Hsiang HUNG
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/04 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/32 , H01L24/73 , H01L2224/02371 , H01L2224/02372 , H01L2224/0392 , H01L2224/0401 , H01L2224/04026 , H01L2224/05025 , H01L2224/05548 , H01L2224/05572 , H01L2224/056 , H01L2224/05687 , H01L2224/0569 , H01L2224/06181 , H01L2224/13022 , H01L2224/13024 , H01L2224/32225 , H01L2224/73153 , H01L2924/00013 , H01L2924/00014 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2924/00012 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要： An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening.
摘要翻译：本发明的实施例提供一种芯片封装，其包括具有第一表面和第二表面的基板; 位于所述第一表面上的导电垫结构; 位于所述基板的所述第一表面上的电介质层和所述导电焊盘结构，其中所述电介质层具有暴露所述导电焊盘结构的一部分的开口; 以及位于电介质层上并填充到开口中的盖层。

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