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    • 4. 发明授权
    • Multi pole piezoelectrically operating relay
    • 多极压电操作继电器
    • US4654555A
    • 1987-03-31
    • US646546
    • 1984-09-04
    • Masatoshi OhbaRyuichi SatoTsutomu Taniguchi
    • Masatoshi OhbaRyuichi SatoTsutomu Taniguchi
    • H01H57/00H01L41/08
    • H01H57/00
    • This multi pole relay includes: a base plate; several bimorphic elements each of elongate plate shape and including a central electrode of elongate plate shape, a pair of piezoelectric members of elongate thin plate shape arranged on opposite sides of the central electrode, and a pair of surface electrodes arranged on the outer surfaces of the pair of piezoelectric members; a means for fixedly mounting the one ends of the bimorphic elements to the base plate with their other ends free; and, for each one of the bimorphic elements: a fixed contact mounted to the base plate opposing the free end of that one of the bimorphic elements; a flexible element, one end of which is mounted to the base plate, and the other free end of which is interposed between the free end of that one of the bimorphic elements and the fixed contact; and a movable contact mounted on the free end of the flexible element on its side towards the fixed contact and opposing the fixed contact. Thereby, the relay may be made very compact and of very low profile, and accordingly is suitable for fitting to a printed circuit board in conjunction with integrated circuits.
    • 该多极继电器包括:基板; 一些细长板形状的双相元件,包括细长板形状的中心电极,一对布置在中心电极的相对侧上的细长薄板形状的压电元件,以及一对表面电极, 一对压电元件; 用于将双相元件的一端固定地安装到底板上的装置,其另一端是自由的; 并且对于每个双相元件:固定触点,其安装到与所述双相元件中的一个元件的自由端相对的基板; 一个柔性元件,其一端安装到基板上,另一端自由端置于该一个双相元件的自由端和固定触点之间; 以及可动触头,其安装在柔性元件的自由端的侧面朝向固定触点并与固定触点相对。 因此,继电器可以制造得非常紧凑并且非常低的轮廓,因此适合于与集成电路一起装配到印刷电路板。
    • 6. 发明授权
    • Communication system and method, and storage medium for the system
    • 通信系统和方法,以及系统的存储介质
    • US07046392B2
    • 2006-05-16
    • US09833989
    • 2001-04-12
    • Tetsuya ShibataShigeki NakaharaTamotsu ShutoMakoto NakabayashiTsutomu TaniguchiKatsumi Nagata
    • Tetsuya ShibataShigeki NakaharaTamotsu ShutoMakoto NakabayashiTsutomu TaniguchiKatsumi Nagata
    • G06F15/00
    • H04N1/32448H04N1/21H04N1/32358
    • A communication system serving as a transmitter terminal and a receiver terminal for communications with a second communication system via a communication line, the communication system includes a storage section for data storage; a communication section for data communications, the communication section being adapted for reception and transmission of data and size information indicative of the size of the data with respect to the second communication system; a detection section for detecting a free space in the storage section; a comparing section for comparing the data size contained in the size information with the size of the free space in the storage section; a calculating section for, if the storage section is short of free space for accommodation of the data size, calculating a waiting period required for recovery from the shortage of the free space in the storage section; and a timer section for timing the lapse of the waiting period.
    • 一种用作发射机终端的通信系统和用于经由通信线路与第二通信系统通信的接收机终端,所述通信系统包括用于数据存储的存储部分; 用于数据通信的通信部分,所述通信部分适于接收和发送指示相对于第二通信系统的数据大小的数据和大小信息; 检测部,其检测所述存储部的自由空间; 比较部分,用于将包含在尺寸信息中的数据大小与存储部分中的自由空间的大小进行比较; 计算部,如果所述存储部分缺少用于容纳所述数据大小的可用空间,则计算从所述存储部分中的所述可用空间不足而要求恢复的等待期; 以及用于对等待时间的过去进行定时的定时器部分。
    • 8. 发明授权
    • Semiconductor memory device, circuit board mounted with semiconductor memory device, and method for testing interconnection between a semiconductor memory device with a circuit board
    • 半导体存储器件,安装有半导体存储器件的电路板以及用于测试半导体存储器件与电路板之间的互连的方法
    • US06208571B1
    • 2001-03-27
    • US09500467
    • 2000-02-09
    • Mitsutaka IkedaTsutomu TaniguchiYoshikazu Homma
    • Mitsutaka IkedaTsutomu TaniguchiYoshikazu Homma
    • G11C700
    • G01R31/31717G01R31/2853G01R31/31701G01R31/31905
    • A semiconductor memory device comprises a detecting unit and a testing unit. The detecting unit detects a plurality of times a state of a predetermined terminal when the power is switched on, and activates the testing unit when all results of the detections show expected values. The device shifts to a connection testing mode by activation of the testing unit, and performs predetermined testing. Therefore, the testing can be performed by causing the device to shift to the testing mode without using terminals dedicated to testing. Besides, a shift to the connection testing mode by activation due to an erroneous operation or power-supply noise is prevented from occurring. In another semiconductor memory device the conversion circuit receives parallel testing patterns via a plurality of input terminals and converts the patterns into serial output patterns. Since the parallel testing patterns are converted into serial output patterns, connection testing can be performed even when the number of output terminals is small. Furthermore, another semiconductor memory device comprises an operation circuit and a conversion circuit. The operation circuit receives parallel testing patterns via a plurality of input terminals, performs a logic operation, and outputs parallel operation result patterns. The conversion circuit receives the parallel operation result patterns and converts the patterns into serial output patterns. The converted output patterns are sequentially output from output terminals. The testing patterns fed to the conversion circuit by the operation circuit can be reduced. Accordingly, the output patterns become shorter, and testing time is reduced.
    • 半导体存储器件包括检测单元和检测单元。 当所述电源接通时,所述检测单元多次检测预定终端的状态,并且当所有检测结果显示预期值时激活测试单元。 设备通过激活测试单元而转换到连接测试模式,并执行预定的测试。 因此,可以通过使设备转移到测试模式而不使用专用于测试的终端来进行测试。 此外,防止由于错误的操作或电源噪声的激活而转换到连接测试模式。 在另一个半导体存储器件中,转换电路经由多个输入端子接收并行测试图案,并将该图案转换为串行输出模式。 由于将并行测试模式转换为串行输出模式,即使输出端子数量少,也可进行连接测试。 此外,另一半导体存储器件包括一个操作电路和一个转换电路。 操作电路通过多个输入端子接收并行测试模式,执行逻辑运算,并输出并行运算结果模式。 转换电路接收并行运算结果模式并将模式转换为串行输出模式。 转换的输出图形从输出端依次输出。 可以减少由操作电路馈送到转换电路的测试图案。 因此,输出模式变短,测试时间缩短。