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1. 发明授权

US5409926A AT-2 antagonist inhibition of vascular restenosis 失效
标题翻译： AT-2拮抗剂抑制血管再狭窄
公开(公告)号：US5409926A
公开(公告)日：1995-04-25
申请号：US93833
申请日：1993-07-19
申请人： Christopher F. Reilly , Stephen E. Delaszlo , Robert G. Johnson , Tsuneo Fujita
发明人： Christopher F. Reilly , Stephen E. Delaszlo , Robert G. Johnson , Tsuneo Fujita
IPC分类号： A61K31/505 , A61K31/655
CPC分类号： A61K31/505 , A61K31/655
摘要： Novel disubstituted 6-aminoquinazolinones of the Formula ##STR1## are useful as angiotensin-II receptor (subtype 2) antagonists (AT.sub.2 antagonists) alone or in combination with heparin, and can act to suppress the vascular stenosis which commonly occurs during the development of atherosclerosis and the restenosis following arterial angioplasty, stent placement, bypass surgery, heart transplantation or endarterectomy.
摘要翻译：式（I）的新型二取代的6-氨基喹唑啉酮可单独或与肝素组合用作血管紧张素-II受体（亚型2）拮抗剂（亚型2拮抗剂），并且可用于抑制通常发生在血管狭窄的血管狭窄动脉粥样硬化的发展和动脉血管成形术，支架置入，旁路手术，心脏移植或内膜切除术后的再狭窄。

2. 发明授权

US3978229A Synergistic composition comprising PGF.sub.2.sub..alpha. and PGE.sub.2 失效
标题翻译：包含PGF'2“+ 0和PGE'2的协同组合物
公开(公告)号：US3978229A
公开(公告)日：1976-08-31
申请号：US566146
申请日：1975-04-08
申请人： Kimiichiro Matsumoto , Tsuneo Fujita , Toshitaka Sakai , Takeshi Tsuda
发明人： Kimiichiro Matsumoto , Tsuneo Fujita , Toshitaka Sakai , Takeshi Tsuda
IPC分类号： A61K47/48 , C07C405/00 , C07D307/935 , C07D309/12 , C07F9/40 , A61K31/19 , A61K31/215 , A61K31/715
CPC分类号： C07D307/935 , A61K47/48969 , B82Y5/00 , C07C405/00 , C07D309/12 , C07F9/4006 , C07F9/4015 , C07F9/4018
摘要： A synergistic composition comprising as active ingredients a PGF.sub.2.sub..alpha. compound or its cyclodextrin clathrate thereof and a PGE.sub.2 compound or its cyclodextrin clathrate thereof, at a weight ratio of from about 1:0.33 to about 1:1.

3. 发明授权

US5051707A Gain control circuit for amplifier having stepwise variable gain 失效
标题翻译：具有逐步可变增益的放大器增益控制电路
公开(公告)号：US5051707A
公开(公告)日：1991-09-24
申请号：US300070
申请日：1989-01-19
申请人： Tsuneo Fujita
发明人： Tsuneo Fujita
IPC分类号： H03G3/20 , H03G3/30
CPC分类号： H03G3/30 , H03G3/001
摘要： A gain control circuit for an amplifier having a stepwise variable gain is disclosed, which includes a peak detector detecting and holding a peak value of an output voltage of the amplifier, a reference voltage generator generating first and second reference voltages having values different from each other, a comparator circuit comparing the peak value with the first and second reference voltages, and a control circuit responding to a comparison output derived from the comparator circuit and controlling the gain of the amplifier one step by one step such that the peak value becomes to intervene between the first and second reference voltages. When the peak value exists between the first and second reference voltages, the control circuit holds the gain of the amplifier at the current value, so that the amplitude of the output voltage is controlled to be substantially constant.

4. 发明授权

US4644322A Analog-to-digital converter 失效
标题翻译：模数转换器
公开(公告)号：US4644322A
公开(公告)日：1987-02-17
申请号：US435965
申请日：1982-10-22
申请人： Tsuneo Fujita
发明人： Tsuneo Fujita
IPC分类号： H03M1/36 , H03M1/00 , H03M7/16
CPC分类号： H03M1/1071 , H03M1/361
摘要： A parallel comparison type A/D converter comprises a voltage divider having 2.sup.N divider junctions connected in series between a reference voltage terminal and a ground potential terminal, 2.sup.N comparators for receiving as reference voltages the outputs of the respective divider junctions, a position detection logic circuit for receiving the outputs of the comparators, an encoder for receiving the output of the position detection logic circuit, and a code converter for receiving the output of the first digital encoder. The encoder adopts the Gray code format, and the code converter converts the Gray code format into the binary code format.
摘要翻译：并联比较型A / D转换器包括：一个分压器，具有2N个分压器串联连接在一个参考电压端子和一个地电位端子之间; 2N个比较器，用于接收相应的分压器结点的输出作为参考电压，一个位置检测逻辑电路用于接收比较器的输出，用于接收位置检测逻辑电路的输出的编码器和用于接收第一数字编码器的输出的代码转换器。编码器采用格雷码格式，代码转换器将格雷码格式转换为二进制码格式。

5. 发明授权

US4596978A Parallel comparison type analog to digital converter 失效
标题翻译：并行比较型模数转换器
公开(公告)号：US4596978A
公开(公告)日：1986-06-24
申请号：US590618
申请日：1984-03-19
申请人： Tsuneo Fujita
发明人： Tsuneo Fujita
IPC分类号： H03M1/36 , H03M1/00
CPC分类号： H03M1/0809 , H03M1/365
摘要： A parallel comparison type A/D converter which can produce a digital output with improved monotonic operation.The A/D converter comprises a plurality of comparators for comparing an analog signal with a plurality comparison voltage, and a plurality of logic gates each having a first input terminal of a positive logic and a second input terminal of a negative logic, one of the first and second input terminals receiving an outpt signal from one of the comparators of a certain weight and the other of the first and second input terminals receiving an output signal from the comparator having a weight subsequent to the certain weight. The threshold values of the first and second input terminals are made different from each other.
摘要翻译：一种并行比较型A / D转换器，可以产生具有改进的单调操作的数字输出。 A / D转换器包括用于将模拟信号与多个比较电压进行比较的多个比较器，以及多个逻辑门，每个具有正逻辑的第一输入端和负逻辑的第二输入端，第一和第二输入端子接收来自某一权重的比较器中的一个输出信号，而第一和第二输入端子中的另一个接收来自具有一定重量之后的权重的比较器的输出信号。使第一和第二输入端子的阈值彼此不同。

6. 发明授权

US4987323A Peak voltage holding circuit 失效
标题翻译：峰值电压保持电路
公开(公告)号：US4987323A
公开(公告)日：1991-01-22
申请号：US385818
申请日：1989-07-27
申请人： Tsuneo Fujita
发明人： Tsuneo Fujita
IPC分类号： G01R19/04
CPC分类号： G01R19/04
摘要： In a peak voltage holding circuit, a leakage circuit includes a first-stage mirror circuit, a second-stage mirror circuit, a selecting circuit, a capacitor, and a control circuit. The first-stage mirror circuit has one end connected to a second potential. The second-stage mirror circuit has one end connected to the output side of an input circuit and the other end connected to a first potential, and causes a current corresponding to a current which flows through the first-stage mirror circuit connected to the first potential to flow out from the voltage holding capacitor. The selecting circuit is connected the other end of the first-stage mirror circuit. The capacitor has one end connected to the selecting circuit and the other end connected to the first potential. The control circuit is connected to the selecting circuit and controls an operation of the selecting circuit. The selecting circuit alternately connects one end of the capacitor to the other end of the first-stage mirror circuit and the first potential at every arbitrary period.
摘要翻译：在峰值电压保持电路中，泄漏电路包括第一级镜电路，第二级镜电路，选择电路，电容器和控制电路。第一级镜电路的一端连接到第二电位。第二级镜电路的一端连接到输入电路的输出侧，另一端连接到第一电位，并且引起与流过连接到第一电位的第一级镜电路的电流相对应的电流从保压电容器流出。选择电路连接在第一级镜电路的另一端。电容器的一端连接到选择电路，另一端连接到第一电位。控制电路连接到选择电路并控制选择电路的操作。选择电路在每个任意时段将电容器的一端交替地连接到第一级反射镜电路的另一端和第一电位。

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