专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090313315A1 N-digit subtraction unit, N-digit subtraction module, N-digit addition unit and N-digit addition module 有权
标题翻译： N位减法单元，N位减法模块，N位加法单元和N位加法模块
公开(公告)号：US20090313315A1
公开(公告)日：2009-12-17
申请号：US12196002
申请日：2008-08-21
申请人： Hiroshi Kasahara , Tsugio Nakamura , Jin Sato
发明人： Hiroshi Kasahara , Tsugio Nakamura , Jin Sato
IPC分类号： G06F7/50
CPC分类号： G06F7/505
摘要： Provided are N-digit addition and subtraction units and N-digit addition and subtraction modules in which borrowing and carrying are not propagated in modules having basic digits. In the units and modules, an output pattern of results of addition and subtraction is predicted based on a relation between an augend and an addend and a relation between a minuend and a subtrahend, respectively, thereby preventing borrowing and carrying from being propagated in modules having basic digits.
摘要翻译：提供了N位加减单元和N位加减模块，其中借用和携带不在具有基本数字的模块中传播。在单元和模块中，基于加法和加数之间的关系以及分支和减数之间的关系来预测加法和减法的结果的输出模式，从而防止借用和携带在具有基本数字

2. 发明授权

US07117237B2 Information processing system, encryption/decryption system, system LSI, and electronic equipment 失效
标题翻译：信息处理系统，加密/解密系统，系统LSI和电子设备
公开(公告)号：US07117237B2
公开(公告)日：2006-10-03
申请号：US10375995
申请日：2003-02-28
申请人： Kazuhiko Amano , Tsugio Nakamura , Hiroshi Kasahara , Tatsuya Shimoda
发明人： Kazuhiko Amano , Tsugio Nakamura , Hiroshi Kasahara , Tatsuya Shimoda
IPC分类号： G06F7/38
CPC分类号： G06F7/57 , G06F7/535 , G06F7/723 , G06F21/72 , G06F2207/3816 , G06F2207/5353 , G06F2221/2149
摘要： An information processing system that is configured in such a manner that computational processing is performed on input data in accordance with a processing sequence, for outputting data, comprises: a plurality of arithmetic units (7-1 to 7-x), each computing at an arithmetic precision 2m bits (where m is a natural number) based on the processing sequence; and a plurality of cascade connection terminals for cascading these arithmetic units each other. When the maximum arithmetic precision that is required during computational processing is 2n bits (where n is a natural number and is fixed), x numbers of (where x is a natural number) the arithmetic units are cascaded in a manner such that the inequality x≧2n/2m is satisfied. When an arithmetic precision of 2n1 bits (where n1≦n, and n1 is variable) is necessary during computational processing, x1 numbers of the arithmetic units are cascaded in a manner such that the inequality x1≧2n1/2m (where x1 is a natural number and is variable) is satisfied. This makes it possible to easily implement an information processing system for performing computations to any desired precision in a hardware manner, and also makes it possible to support a simple hardware-based method of expanding the arithmetic precision.
摘要翻译：一种信息处理系统，其被配置为使得根据用于输出数据的处理序列对输入数据进行计算处理的方式包括：多个运算单元（7-1至7-x），每个运算单元基于处理顺序的算术精度2 位（其中m是自然数）以及用于将这些算术单元彼此级联的多个级联连接端子。当计算处理期间所需的最大算术精度为2个比特（其中n是自然数并且是固定的）时，算术单元级联的（其中x是自然数）的x个数以满足不等式x> = 2 / 2 的方式。当在计算处理期间需要2×n1位的运算精度（其中n1 <= n和n1是可变的）时，运算单元的x1个数以这样的方式级联，使得不等式x1> = 2＆lt; n1＆lt; / 2＆gt;（其中x1是自然数并且是可变的）。这使得可以容易地实现用于以硬件方式执行任何期望精度的计算的信息处理系统，并且还可以支持扩展算术精度的简单的基于硬件的方法。

3. 发明授权

US4118892A Connectable nursery box structures having compartmentalizing grids 失效
标题翻译：具有分隔网格的可连接的托儿所结构
公开(公告)号：US4118892A
公开(公告)日：1978-10-10
申请号：US765479
申请日：1977-02-04
申请人： Tsugio Nakamura , Seigo Aizaki , Kosei Hayashi
发明人： Tsugio Nakamura , Seigo Aizaki , Kosei Hayashi
IPC分类号： A01G9/10 , A01G9/02 , A01G9/12
CPC分类号： A01G9/025 , A01G1/007 , A01G9/104 , Y02P60/244
摘要： A molded synthetic resin nursery box B comprises a grid member 2 dividing the box into individual compartments 3 communicating with each other through side wall apertures 23. A wavy bottom plate 12 of the box has drainage holes 13 therein, and the grid member side walls are notched at their top edges. Adjacent boxes are connected by engaging projections 4 on one box with mating slots 5 on another box. The planted boxes may be installed on a horizontal surface whereby the grid members bear the weight of a person walking thereon to prevent trampling and plant damage, or vertically by mounting the boxes in assembled, stacked frames 100 filled with soil. Alternatively, the grid members may be made separate from the bottom plate and side wall 11 bases, and snap-connected to pedestals 14 upstanding from the bottom plates after planting.
摘要翻译：模制合成树脂苗圃箱B包括格栅构件2，该格栅构件2将箱分成通过侧壁孔23彼此连通的单个隔间3.箱的波浪底板12在其中具有排水孔13，并且栅格构件侧壁在他们的顶部边缘切口。相邻的盒子通过将一个盒子上的突起4接合在另一个盒子上的配合槽5来连接。种植的盒子可以安装在水平表面上，由此网格构件承受在其上行走的人的重量，以防止践踏和植物损坏，或者通过将盒子安装在填充有土壤的组装的堆叠框架100中。或者，网格构件可以从底板和侧壁11基座分离制成，并且在植入之后卡扣连接到从底板直立的基座14。

4. 发明授权

US3944282A Article of furniture formed by interconnected structural bodies 失效
标题翻译：由相互联系的结构体组成的家具制品
公开(公告)号：US3944282A
公开(公告)日：1976-03-16
申请号：US501859
申请日：1974-08-30
申请人： Tsugio Nakamura
发明人： Tsugio Nakamura
IPC分类号： A47B13/00 , A47C3/16 , A47C4/02 , A47C13/00 , A47C7/00
CPC分类号： A47C13/005 , A47C3/16
摘要： An article of furniture is formed by a plurality of structural members connected to one another. Each of the structural members comprises an angulated barrel-shaped frame body consisting of a pair of spaced, opposed frame plates which narrow in width from the central portion towards the opposite ends thereof, and another pair of opposed frame plates of constant width over the entire length thereof. Wall plates cover the frame body. A plurality of such structural members are connected with one another by the aid of connecting members disposed substantially in the central portion of the structural member to form furniture such as sofas, desks, beds, tables, etc.
摘要翻译：一种家具由多个彼此连接的结构构件形成。每个结构构件包括一个角形的桶形框架体，由一对间隔开的相对的框架板组成，其宽度从中心部分朝向其相对端窄，另一对整体上具有恒定宽度的相对的框架板长度。墙板覆盖框架体。多个这样的结构构件通过基本上设置在结构构件的中心部分的连接构件彼此连接，以形成诸如沙发，书桌，床，桌子等的家具。

5. 发明授权

US08606842B2 N-digit subtraction unit, N-digit subtraction module, N-digit addition unit and N-digit addition module 有权
公开(公告)号：US08606842B2
公开(公告)日：2013-12-10
申请号：US12196002
申请日：2008-08-21
申请人： Hiroshi Kasahara , Tsugio Nakamura , Jin Sato
发明人： Hiroshi Kasahara , Tsugio Nakamura , Jin Sato
IPC分类号： G06F7/50
CPC分类号： G06F7/505
摘要： Provided are N-digit addition and subtraction units and N-digit addition and subtraction modules in which borrowing and carrying are not propagated in modules having basic digits. In the units and modules, an output pattern of results of addition and subtraction is predicted based on a relation between an augend and an addend and a relation between a minuend and a subtrahend, respectively, thereby preventing borrowing and carrying from being propagated in modules having basic digits.

6. 发明授权

US06557020B1 Information processing system, enciphering/deciphering system, system LSI, and electronic apparatus 失效
标题翻译：信息处理系统，加密/解密系统，系统LSI和电子设备
公开(公告)号：US06557020B1
公开(公告)日：2003-04-29
申请号：US09367234
申请日：1999-10-13
申请人： Kazuhiko Amano , Tsugio Nakamura , Hiroshi Kasahara , Tatsuya Shimoda
发明人： Kazuhiko Amano , Tsugio Nakamura , Hiroshi Kasahara , Tatsuya Shimoda
IPC分类号： G06F738
CPC分类号： G06F7/57 , G06F7/535 , G06F7/723 , G06F21/72 , G06F2207/3816 , G06F2207/5353 , G06F2221/2149
摘要： An information processing system that is configured in such a manner that computational processing is performed on input data in accordance with a processing sequence, for outputting data, comprises: a plurality of arithmetic units (7-1 to 7-x), each computing at an arithmetic precision 2m bits (where m is a natural number) based on the processing sequence; and a plurality of cascade connection terminals for cascading these arithmetic units each other. When the maximum arithmetic precision that is required during computational processing is 2n bits (where n is a natural number and is fixed), x numbers of (where x is a natural number) the arithmetic units are cascaded in a manner such that the inequality x≧2n/2m is satisfied. When an arithmetic precision of 2n1 bits (where n1≦n, and n1 is variable) is necessary during computational processing, x1 numbers of the arithmetic units are cascaded in a manner such that the inequality x1≧2n1/2m (where x1 is a natural number and is variable) is satisfied. This makes it possible to easily implement an information processing system for performing computations to any desired precision in a hardware manner, and also makes it possible to support a simple hardware-based method of expanding the arithmetic precision.
摘要翻译：一种信息处理系统，其被配置为使得根据用于输出数据的处理序列对输入数据进行计算处理的方式包括：多个运算单元（7-1至7-x），每个运算单元基于处理顺序的算术精度为2m比特（其中m为自然数）以及用于将这些算术单元彼此级联的多个级联连接端子。当计算处理期间所需的最大算术精度是2n位（其中n是自然数并且是固定的）时，运算单元的x数（其中x是自然数）是以不等式x > = 2n / 2m。当计算处理期间需要2n1位（其中n1 <= n和n1是可变的）的算术精度时，以不等式x1> = 2n1 / 2m（其中x1为自然数和变量）是满足的。这使得可以容易地实现用于以硬件方式执行任何期望精度的计算的信息处理系统，并且还可以支持扩展算术精度的简单的基于硬件的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式