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1. 发明授权

US06347063B1 Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof 有权
标题翻译：半导体存储器件包括形成在公共芯片上的动态型存储器和静态型存储器及其操作方法
公开(公告)号：US06347063B1
公开(公告)日：2002-02-12
申请号：US09618568
申请日：2000-07-17
申请人： Katsumi Dosaka , Toshiyuki Omoto , Masaki Kumanoya
发明人： Katsumi Dosaka , Toshiyuki Omoto , Masaki Kumanoya
IPC分类号： G11C800
CPC分类号： G06F12/0893 , G11C11/005
摘要： A semiconductor memory device which is applicable not only to a cache system but to the field of graphic processing is provided. The semiconductor memory device includes a DRAM portion, an SRAM portion and a bidirectional data transfer circuit 106 which carries out data transfer between a DRAM array included in the DRAM portion and an SRAM array included in the SRAM portion as well as data input/output with the outside of the device. Driving of the DRAM array and data transfer operation between the DRAM array and the bidirectional data transfer circuit are controlled by a DRAM control circuit. Driving of the SRAM array, data transfer between the SRAM array and the bidirectional data transfer circuit, and the data input/output operation are controlled by the SRAM control circuit. The address to the DRAM array is applied to a DRAM array buffer 108, while an address for selecting a memory cell in the SRAM array is applied to the SRAM address buffer.
摘要翻译：提供了一种半导体存储器件，其不仅可应用于缓存系统，还适用于图形处理领域。半导体存储器件包括DRAM部分，SRAM部分和双向数据传输电路106，其执行DRAM部分中包括的DRAM阵列与SRAM部分中包括的SRAM阵列之间的数据传输以及数据输入/输出设备的外部。 DRAM阵列的驱动和DRAM阵列与双向数据传输电路之间的数据传送操作由DRAM控制电路控制。 SRAM阵列的驱动，SRAM阵列和双向数据传输电路之间的数据传输以及数据输入/输出操作由SRAM控制电路控制。将DRAM阵列的地址应用于DRAM阵列缓冲器108，而用于选择SRAM阵列中的存储单元的地址被施加到SRAM地址缓冲器。

2. 发明授权

US6151269A Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof 失效
公开(公告)号：US6151269A
公开(公告)日：2000-11-21
申请号：US007229
申请日：1998-01-14
申请人： Katsumi Dosaka , Toshiyuki Omoto , Masaki Kumanoya
发明人： Katsumi Dosaka , Toshiyuki Omoto , Masaki Kumanoya
IPC分类号： G06F12/08 , G11C11/00 , G11C11/401 , G11C11/407 , G11C11/409 , G11C11/41 , G11C8/00
CPC分类号： G06F12/0893 , G11C11/005
摘要： A semiconductor memory device which is applicable not only to a cache system but to the field of graphic processing is provided. The semiconductor memory device includes a DRAM portion, an SRAM portion and a bidirectional data transfer circuit 106 which carries out data transfer between a DRAM array included in the DRAM portion and an SRAM array included in the SRAM portion as well as data input/output with the outside of the device. Driving of the DRAM array and data transfer operation between the DRAM array and the bidirectional data transfer circuit are controlled by a DRAM control circuit. Driving of the SRAM array, data transfer between the SRAM array and the bidirectional data transfer circuit, and the data input/output operation are controlled by the SRAM control circuit. The address to the DRAM array is applied to a DRAM array buffer 108, while an address for selecting a memory cell in the SRAM array is applied to the SRAM address buffer.

3. 发明授权

US5777942A Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof 失效
公开(公告)号：US5777942A
公开(公告)日：1998-07-07
申请号：US149680
申请日：1993-11-08
申请人： Katsumi Dosaka , Toshiyuki Omoto , Masaki Kumanoya
发明人： Katsumi Dosaka , Toshiyuki Omoto , Masaki Kumanoya
IPC分类号： G06F12/08 , G11C11/00 , G11C11/401 , G11C11/407 , G11C11/409 , G11C11/41 , G11C8/00
CPC分类号： G06F12/0893 , G11C11/005
摘要： A semiconductor memory device which is applicable not only to a cache system but to the field of graphic processing is provided. The semiconductor memory device includes a DRAM portion, an SRAM portion and a bidirectional data transfer circuit 106 which carries out data transfer between a DRAM array included in the DRAM portion and an SRAM array included in the SRAM portion as well as data input/output with the outside of the device. Driving of the DRAM array and data transfer operation between the DRAM array and the bidirectional data transfer circuit are controlled by a DRAM control circuit. Driving of the SRAM array, data transfer between the SRAM array and the bidirectional data transfer circuit, and the data input/output operation are controlled by the SRAM control circuit. The address to the DRAM array is applied to a DRAM array buffer 108, while an address for selecting a memory cell in the SRAM array is applied to the SRAM address buffer.

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