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    • 2. 发明申请
    • Stress Measurement Kit and Stress Measurement Method
    • 应力测量套件和应力测量方法
    • US20100206748A1
    • 2010-08-19
    • US12670531
    • 2008-07-31
    • Mitsuhiro MoritaToshiaki BabaHiroshi YoshidaEmi Nishimura
    • Mitsuhiro MoritaToshiaki BabaHiroshi YoshidaEmi Nishimura
    • G01N27/327
    • G01N27/3273A61B10/0051C12Q1/005
    • Provided is a stress measurement kit that is economical and that has good sensitivity. The stress measurement kit for measuring a stress level of a test subject includes: (A) a sensor chip including an electrically insulating substrate, and an electrode system that is placed on the electrically insulating substrate and that includes at least a working electrode and a counter electrode, wherein glucose dehydrogenase (GDH) and an electron mediator are immobilized on the working electrode; (B) a polysaccharide; and (C) a sensor body including an insertion hole into which the sensor chip is inserted, an electrical measurement means that is electrically connected to the electrode system of the sensor chip in a state where the sensor chip is inserted into the insertion hole, and a conversion means by which a current value or an electric quantity measured by the electrical measurement means is converted into an amylase activity value.
    • 提供了一种经济且具有良好灵敏度的应力测量套件。 用于测量受检对象的应力水平的应力测量套件包括:(A)包括电绝缘衬底的传感器芯片和放置在电绝缘衬底上并且至少包括工作电极和计数器的电极系统 电极,其中葡萄糖脱氢酶(GDH)和电子介体固定在工作电极上; (B)多糖; 和(C)传感器本体,其包括插入有传感器芯片的插入孔,在传感器芯片插入插入孔的状态下电连接到传感器芯片的电极系统的电测量装置,以及 将通过电测量装置测量的电流值或电量转换成淀粉酶活性值的转换装置。
    • 4. 发明授权
    • Test circuit for semiconductor integrated circuit
    • 半导体集成电路测试电路
    • US07712002B2
    • 2010-05-04
    • US11592163
    • 2006-11-03
    • Toshiaki Baba
    • Toshiaki Baba
    • G01R31/28
    • G01R31/318594
    • The present invention provides a test circuit for a semiconductor integrated circuit that can be used for testing plural of logic blocks each having plural input-output terminals. This test circuit is provided with scanning flip-flop (SFF) circuits whose output terminals are connected to the input terminals of the logic blocks. The SFF circuits hold test data which is sequentially supplied, supply the test data to the logic blocks and receive logic operation data generated from the logic blocks. The logic operation data may be sequentially supplied from the SFF circuits, on the basis of which performances of the logic blocks are examined.
    • 本发明提供一种用于半导体集成电路的测试电路,其可用于测试多个具有多个输入 - 输出端子的逻辑块。 该测试电路设有扫描触发器(SFF)电路,其输出端连接到逻辑块的输入端。 SFF电路保存顺序提供的测试数据,将测试数据提供给逻辑块,并接收从逻辑块生成的逻辑运算数据。 逻辑运算数据可以从SFF电路依次检查逻辑块的性能来依次提供。
    • 5. 发明授权
    • Photovoltaic element and photovoltaic device
    • 光伏元件和光伏器件
    • US07214872B2
    • 2007-05-08
    • US10245087
    • 2002-09-17
    • Eiji MaruyamaToshiaki Baba
    • Eiji MaruyamaToshiaki Baba
    • H01L31/00
    • H01L31/022475
    • An ITO film as a transparent conductive film is formed on a semiconductor layer comprising an amorphous semiconductor or a microcrystalline semiconductor, a comb-like collecting electrode is formed on the ITO film, and a cover glass containing alkaline ions is placed on the ITO film and collecting electrode with a resin film made of EVA between them. The (222) plane orientation degree of the ITO film (transparent conductive film) is not less than 1.0, preferably not less than 1.2 and not more than 2.6, and more preferably not less than 1.4 and not more than 2.5. Alternatively, the transparent conductive film has an orientation of (321) planes on the boundary side with respect to the semiconductor layer and mainly an orientation of (222) planes in the remaining portion. When the total thickness of the ITO film is 100 nm, the (321)/(222) diffraction strength ratio in a 10 nm-thick portion on the semiconductor layer side is not less than 0.5 and not more than 2.5.
    • 在包括非晶半导体或微晶半导体的半导体层上形成作为透明导电膜的ITO膜,在ITO膜上形成梳状收集电极,将含有碱离子的覆盖玻璃放置在ITO膜上, 在它们之间用EVA制成的树脂膜收集电极。 ITO膜(透明导电膜)的(222)面取向度为1.0以上,优选为1.2以上且2.6以下,更优选为1.4以上且2.5以下。 或者,透明导电膜在边界侧相对于半导体层具有取向(321)面,主要在其余部分具有(222)面的取向。 当ITO膜的总厚度为100nm时,半导体层侧的10nm厚的部分的(321)/(222)衍射强度比不小于0.5且不大于2.5。
    • 7. 发明授权
    • Method of designing conductive pattern layout of LSI
    • LSI的导电图案布局设计方法
    • US06609240B2
    • 2003-08-19
    • US09984839
    • 2001-10-31
    • Toshiaki Baba
    • Toshiaki Baba
    • G06F1750
    • G06F17/5068
    • There is provided a method of designing a conductive pattern layout between a plurality of blocks in an LSI, the conductive pattern transferring data from one block to the other blocks, comprising: (a) extracting the blocks from logic circuit data; (b) preparing a floor plan which defines a provisional arrangement of the blocks; (c) arranging a plurality of conductive pattern cells between the plurality of blocks after preparing the floor plan; (d) re-arranging the blocks on the basis of the arrangement of the conductive pattern cells; (e) arranging a plurality of power source patterns; and (g) arranging a plurality of signal patterns. Due to this conductive pattern layout and method of designing thereof, wiring between blocks can be carried out simply and with high accuracy.
    • 提供了一种在LSI中的多个块之间设计导电图案布局的方法,所述导电图案将数据从一个块传送到其他块,包括:(a)从逻辑电路数据中提取块; (b)制定一项界定一个临时安排的楼层平面图; (c)在准备所述平面图之后,在所述多个块之间布置多个导电图案单元; (d)基于导电图案单元的布置重新布置块; (e)布置多个电源图案; 和(g)排列多个信号图形。 由于该导电图案布局及其设计方法,可以简单且高精度地执行块之间的布线。
    • 8. 发明申请
    • Test circuit for semiconductor integrated circuit
    • 半导体集成电路测试电路
    • US20070143652A1
    • 2007-06-21
    • US11592163
    • 2006-11-03
    • Toshiaki Baba
    • Toshiaki Baba
    • G01R31/28
    • G01R31/318594
    • The present invention provides a test circuit for a semiconductor integrated circuit that can be used for testing plural of logic blocks each having plural input-output terminals. This test circuit is provided with scanning flip-flop (SFF) circuits whose output terminals are connected to the input terminals of the logic blocks. The SFF circuits hold test data which is sequentially supplied, supply the test data to the logic blocks and receive logic operation data generated from the logic blocks. The logic operation data may be sequentially supplied from the SFF circuits, on the basis of which performances of the logic blocks are examined.
    • 本发明提供一种用于半导体集成电路的测试电路,其可用于测试多个具有多个输入 - 输出端子的逻辑块。 该测试电路设有扫描触发器(SFF)电路,其输出端连接到逻辑块的输入端。 SFF电路保存顺序提供的测试数据,将测试数据提供给逻辑块,并接收从逻辑块生成的逻辑运算数据。 逻辑运算数据可以从SFF电路依次检查逻辑块的性能来依次提供。
    • 10. 发明授权
    • Solar cell module
    • 太阳能电池组件
    • US09159859B2
    • 2015-10-13
    • US12375768
    • 2007-07-31
    • Toshiaki Baba
    • Toshiaki Baba
    • H01L31/00H01L31/05H01L31/0224H01L31/042H01L31/02
    • H01L31/0504H01L31/02013H01L31/042Y02E10/50
    • Disclosed is a solar cell module including: a plurality of solar cell units each including a supporting substrate 30 and an even number of solar cells 20 disposed on the supporting substrate 30; and a conductor 10 configured to electrically connecting surfaces of adjacent solar cells 20 that have opposite surface polarities and are formed in respective solar cell units adjacent to each other. The solar cells 20 having the opposite surface polarities are alternately arranged in each of the solar cell units so that the surface polarities of the adjacent solar cells 20 are opposite to each other, and the solar cell unit has one or more sets of two solar cells electrically connected to each other on the supporting substrate 30.
    • 公开了一种太阳能电池模块,包括:多个太阳能电池单元,每个太阳能电池单元包括支撑基板30和设置在支撑基板30上的偶数个太阳能电池20; 以及导体10,被配置为将相邻的太阳能电池20的表面极性电连接并形成在彼此相邻的各个太阳能电池单元中。 具有相反表面极性的太阳能电池20交替地布置在每个太阳能电池单元中,使得相邻的太阳能电池20的表面极性彼此相反,并且太阳能电池单元具有一组或多组两个太阳能电池 在支撑基板30上彼此电连接。