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    • 1. 发明申请
    • SUBSTRATE INTER-TERMINAL VOLTAGE SENSING CIRCUIT
    • 基板端子间电感传感电路
    • US20110199224A1
    • 2011-08-18
    • US13029417
    • 2011-02-17
    • Tomohiko TATSUMI
    • Tomohiko TATSUMI
    • G08B21/00G01R27/08
    • H01L22/34H01L2924/0002H01L2924/00
    • A substrate inter-terminal voltage sensing circuit which can promptly sense a plasma charge-up occurring on a semiconductor wafer across a wide range without connection of a voltage measuring instrument. The substrate inter-terminal voltage sensing circuit is adapted to sense a voltage occurring between a pair of electrodes arranged on a semiconductor substrate. The voltage sensing circuit includes a resistance path that is connected between the electrodes. The voltage sensing circuit also includes a circuit power supply that is connected at one end to a midpoint of the resistance path. The voltage sensing circuit also includes at least two fuse circuits that are connected between one end of the resistance path and the other end of the circuit power supply so as to be in parallel with each other. The fuse circuits have different rated fusing currents from each other. Each of the fuse circuits includes a switch that turns ON or OFF depending on a potential difference between the one end and midpoint of the resistance path. Each fuse circuit also has a current path that is connected across the circuit power supply. The current path possesses a resistive element and a fuse element serially connected to the switch.
    • 一种基板端子间电压检测电路,其能够在不连接电压测量仪器的情况下,在宽范围内及时感测在半导体晶片上发生的等离子体充电。 衬底端子间电压感测电路适于感测在布置在半导体衬底上的一对电极之间出现的电压。 电压检测电路包括连接在电极之间的电阻路径。 电压检测电路还包括在一端连接到电阻路径的中点的电路电源。 电压检测电路还包括至少两个熔丝电路,其连接在电阻路径的一端和电路电源的另一端之间,以彼此平行。 保险丝电路的额定熔断电流彼此不同。 每个保险丝电路包括根据电阻路径的一端和中点之间的电位差而导通或截止的开关。 每个熔丝电路还具有连接在电路电源两端的电流路径。 电流路径具有串联连接到开关的电阻元件和熔丝元件。
    • 2. 发明申请
    • Plasma process detecting sensor
    • 等离子体过程检测传感器
    • US20090061540A1
    • 2009-03-05
    • US12219305
    • 2008-07-18
    • Tomohiko Tatsumi
    • Tomohiko Tatsumi
    • H01L21/00G01R31/00H01L21/302
    • H01L21/67069H01J37/32935H01L21/67253
    • The present invention provides a plasma process detecting sensor. In the plasma process detecting sensor, a hole diameter of an insulating film is spread with almost no spread of a hole diameter of an upper electrode. Therefore, when the plasma process detecting sensor is exposed to a plasma, positive ions incident onto the bottom of a contact hole are hard to collide with an inner wall surface of a hole main body of the insulating film. As a result, the inner wall surface of the hole main body of the insulating film is hard to undergo damage, and the generation of a defect level that assists electric conduction can be suppressed. It is thus possible to suppress age deterioration of a sensor function during the measurement of a charge-up under an environment of a plasma etching condition.
    • 本发明提供一种等离子体处理检测传感器。 在等离子体处理检测传感器中,绝缘膜的孔直径几乎不扩散上部电极的孔直径。 因此,当等离子体处理检测传感器暴露于等离子体时,入射到接触孔底部的正离子难以与绝缘膜的孔主体的内壁表面碰撞。 结果,绝缘膜的孔主体的内壁面难以发生损伤,能够抑制有助于导电的缺陷水平的产生。 因此,可以抑制在等离子体蚀刻条件的环境下的充电测量期间的传感器功能的老化。
    • 3. 发明申请
    • Manufacturing method of semiconductor device
    • 半导体器件的制造方法
    • US20070218609A1
    • 2007-09-20
    • US11705764
    • 2007-02-14
    • Tomohiko Tatsumi
    • Tomohiko Tatsumi
    • H01L21/338
    • H01L29/7923H01L29/66833
    • A gate electrode is formed on a first conductivity type substrate. A second conductivity type implantation region is formed in the first conductivity type substrate. A first conductivity type implantation region is formed by implanting the first conductivity type impurities into the first conductivity type substrate to a depth deeper than the second conductivity type implantation region. An ISSG oxide film whose thickness ranges from 60 nm to 100 nm is formed to cover the first conductivity type substrate and the gate electrode. A silicone nitride film is formed on the ISSG oxide film. A second silicone oxide film is formed on the silicon nitride film. A sidewall is formed to cover the gate electrode and the first conductivity type substrate. A source/drain diffusion layer is formed by implanting second conductivity type impurities into the first conductivity type substrate.
    • 在第一导电型基板上形成栅电极。 在第一导电型衬底中形成第二导电类型注入区。 通过将第一导电类型杂质注入第二导电类型衬底的深度而形成第一导电类型注入区,该深度比第二导电类型注入区深。 形成厚度范围为60nm至100nm的ISSG氧化物膜以覆盖第一导电类型基板和栅电极。 在ISSG氧化膜上形成硅氮化膜。 在氮化硅膜上形成第二氧化硅膜。 形成侧壁以覆盖栅电极和第一导电型基板。 源极/漏极扩散层通过将第二导电型杂质注入到第一导电型衬底中而形成。
    • 5. 发明申请
    • Semiconductor memory device and manufacturing method thereof
    • 半导体存储器件及其制造方法
    • US20080296647A1
    • 2008-12-04
    • US12081633
    • 2008-04-18
    • Tomohiko Tatsumi
    • Tomohiko Tatsumi
    • H01L27/12H01L21/84
    • H01L21/84H01L27/11521H01L27/11558H01L27/1203H01L27/1255H01L29/66825H01L29/7923
    • The present invention provides a semiconductor memory device comprising a semiconductor substrate formed of a support substrate, an insulating film formed over the support substrate and a semiconductor layer formed over the insulating film; a MOSFET having a source layer and a drain layer both formed in the semiconductor layer of a transistor forming area set to the semiconductor substrate, and a channel region provided between the source and drain layers; a MOS capacitor having a capacitor electrode which is formed in the semiconductor layer of a capacitor forming area set to the semiconductor substrate and in which an impurity of the same type as the source layer is diffused; and a device isolation layer which insulates and separates between the semiconductor layer formed with the MOSFET and the semiconductor layer formed with the MOS capacitor, wherein the capacitor electrode of the MOS capacitor is formed in polygon and slanting faces enlarged toward the insulating film are provided therearound, and wherein a floating gate electrode is provided which extends from over a channel region of the MOSEFT to over corners of ends on the MOSFET side, of the capacitor electrode and which is opposite to the channel region and the capacitor electrode with a gate insulating film interposed therebetween.
    • 本发明提供一种半导体存储器件,包括由支撑衬底形成的半导体衬底,形成在支撑衬底上的绝缘膜和形成在绝缘膜上的半导体层; 在半导体衬底的晶体管形成区域的半导体层中形成源极层和漏极层的MOSFET以及设置在源极和漏极层之间的沟道区域; MOS电容器,其具有电容器电极,该电容器电极形成在设置于半导体衬底的电容器形成区域的半导体层中,并且其中与源极层相同类型的杂质扩散; 以及在由MOSFET形成的半导体层与形成有MOS电容器的半导体层之间绝缘并分离的器件隔离层,其中MOS电容器的电容器电极形成为多边形并且朝向绝缘膜扩大的倾斜面设置在其周围 ,并且其中提供浮置栅电极,其从MOSEFT的沟道区域延伸到电容器电极的MOSFET侧的端部的顶角,并且与沟道区域相反,并且具有栅极绝缘膜的电容器电极 插入其间。
    • 7. 发明授权
    • Plasma monitoring method
    • 等离子体监测方法
    • US08427168B2
    • 2013-04-23
    • US12725815
    • 2010-03-17
    • Tomohiko TatsumiSeiji Samukawa
    • Tomohiko TatsumiSeiji Samukawa
    • G01N27/62
    • G01R19/0061H05H1/0081
    • A plasma monitoring method measures in-situ a resistance of and a current flowing in a side wall. A monitoring system has two sensors in a plasma chamber, each having upper and lower electrodes. An external resistance element is connected only to one of the two sensors, in parallel to the wires extending from the upper and lower electrodes of the sensor concerned. Consequently, a resistance between the upper and lower electrodes is different in the two sensors, and two different values of potential difference between the upper and lower electrodes are obtained in-situ. Because a resistance value of the external resistance element is known, a resistance value of a side wall of a contact hole per one contact hole is obtained in-situ, and consequently an electric current flowing in the side wall of the contact hole per one contact hole can be obtained.
    • 等离子体监测方法原位测量在侧壁中流动的电阻和电流。 监测系统在等离子体室中具有两个传感器,每个具有上电极和下电极。 外部电阻元件仅与两个传感器中的一个平行地连接到从相关传感器的上部和下部电极延伸的电线。 因此,两个传感器之间的上下电极之间的电阻是不同的,并且原位获得上下电极之间的两个不同的电位差值。 由于外部电阻元件的电阻值是已知的,所以每个接触孔的接触孔的侧壁的电阻值被原位获得,因此在每个触头的接触孔的侧壁中流动的电流 可以获得孔。
    • 9. 发明申请
    • Plasma monitoring method and plasma monitoring system
    • 等离子体监测方法和等离子体监测系统
    • US20090058424A1
    • 2009-03-05
    • US12219123
    • 2008-07-16
    • Tomohiko TatsumiSeiji Samukawa
    • Tomohiko TatsumiSeiji Samukawa
    • G01N27/62
    • H01J37/32935C23C16/50C23C16/52H01L22/14
    • A plasma monitoring method using a sensor, the sensor having a substrate; a first electrode, the first electrode being a conductive electrode and formed on the substrate while being isolated from the substrate; an insulating film formed on the first electrode; a contact hole formed in the insulating film and having a depth from a surface of the insulating film to the first electrode; and a second electrode, the second electrode being a conductive electrode, formed on the surface of the insulating film, and faced to plasma during a plasma process, the plasma monitoring method including measuring and monitoring potentials of the first electrode and the second electrode or a potential difference between the first electrode and the second electrode during the plasma process is disclosed. A plasma monitoring system carrying out the plasma monitoring method is also disclosed.
    • 使用传感器的等离子体监测方法,所述传感器具有基板; 第一电极,所述第一电极是导电电极,并且形成在所述衬底上,同时与所述衬底分离; 形成在所述第一电极上的绝缘膜; 形成在所述绝缘膜中并具有从所述绝缘膜的表面到所述第一电极的深度的接触孔; 以及第二电极,所述第二电极是形成在所述绝缘膜的表面上并且在等离子体处理期间面向等离子体的导电电极,所述等离子体监测方法包括测量和监测所述第一电极和所述第二电极的电位或 公开了等离子体处理期间第一电极和第二电极之间的电位差。 还公开了进行等离子体监测方法的等离子体监测系统。
    • 10. 发明申请
    • PLASMA MONITORING METHOD
    • 等离子体监测方法
    • US20100244861A1
    • 2010-09-30
    • US12725815
    • 2010-03-17
    • Tomohiko TatsumiSeiji Samukawa
    • Tomohiko TatsumiSeiji Samukawa
    • G01R27/08
    • G01R19/0061H05H1/0081
    • A plasma monitoring method measures in-situ a resistance of a side wall in a particular pattern and a current flowing in the side wall in the pattern. A monitoring system has two sensors in a plasma chamber. Each sensor has an upper electrode and a lower electrode. An external resistance element is connected only to one of the two sensors. The external resistance element is connected in parallel to the wires extending from the upper and lower electrodes of the sensor concerned. As a result, a resistance between the upper and lower electrodes is different in the two sensors, and two different values of potential difference between the upper and lower electrodes are obtained in-situ. Because a resistance value of the external resistance element is already known, a resistance value of a side wall of a contact hole per one contact hole is obtained in-situ. When the resistance per one contact hole is obtained, an electric current flowing in the side wall of the contact hole per one contact hole can be obtained.
    • 等离子体监测方法原位测量特定图案中的侧壁的电阻和在图案中在侧壁中流动的电流。 监测系统在等离子体室中具有两个传感器。 每个传感器具有上电极和下电极。 外部电阻元件仅连接到两个传感器之一。 外部电阻元件与从所述传感器的上部和下部电极延伸的电线并联连接。 结果,两个传感器中的上下电极之间的电阻是不同的,并且原位获得上下电极之间的两个不同的电位差值。 因为外部电阻元件的电阻值是已知的,所以每个接触孔的接触孔的侧壁的电阻值被原位获得。 当获得每个接触孔的电阻时,可以获得在每个接触孔的接触孔的侧壁中流动的电流。