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1. 发明授权

US07954018B2 Analysis techniques for multi-level memory 有权
标题翻译：多级内存分析技术
公开(公告)号：US07954018B2
公开(公告)日：2011-05-31
申请号：US11701700
申请日：2007-02-02
申请人： Tom T. Ho , Jonathan B. Buckheit , Weidong Wang
发明人： Tom T. Ho , Jonathan B. Buckheit , Weidong Wang
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C29/10 , G11C29/56008
摘要： A system and method for defect analysis of multi-level memory cell devices and embedded multi-level memory in system-on-chip integrated circuits are disclosed wherein a defect data set is input into the system. When a defect data set is received, an automated test engineering system running a memory test program analyzes the defect data set to generate one or more fail bit locations and one or more fail states of the memory. The multi-level memory defect analysis system and method then classify failed bits or patterns comprising a vertical fail pattern, whereby after being classified, each memory cell failure vertical fail pattern has three data attributes comprising fail type, a number of fail bits/states, and a sequence of the fail states. The vertical fail pattern may comprise a single fail state or multi-state fail. The multi-state fail may be a continuous-states fail, discontinuous-states fail, or all-state fail. The multi-level memory defect analysis system and method may additionally enable classification of failed bits or patterns comprising a lateral fail pattern. The lateral fail pattern may be a gradual fail pattern, periodic fail pattern, or random fail pattern.
摘要翻译：公开了一种用于系统级芯片集成电路中的多级存储单元器件和嵌入式多级存储器的缺陷分析的系统和方法，其中将缺陷数据集输入到系统中。当接收到缺陷数据集时，运行内存测试程序的自动测试工程系统分析缺陷数据集以生成一个或多个故障位位置和存储器的一个或多个故障状态。多级存储器缺陷分析系统和方法然后对包括垂直故障模式的故障位或模式进行分类，由此在分类之后，每个存储单元故障垂直故障模式具有包括故障类型，多个故障位/状态的三个数据属性，和一系列的失败状态。垂直故障模式可能包含单个故障状态或多状态故障。多状态失败可能是连续状态失败，不连续状态失败或全状态失败。多级存储器缺陷分析系统和方法还可以使得能够对包括横向失效模式的故障位或模式进行分类。横向失效模式可能是逐渐失败模式，周期性失败模式或随机失败模式。

2. 发明授权

US08190952B2 Bitmap cluster analysis of defects in integrated circuits 有权
标题翻译：集成电路缺陷位图聚类分析
公开(公告)号：US08190952B2
公开(公告)日：2012-05-29
申请号：US12728629
申请日：2010-03-22
申请人： Tom T. Ho , Jonathan B. Buckheit , Weidong Wang , Xin Sun
发明人： Tom T. Ho , Jonathan B. Buckheit , Weidong Wang , Xin Sun
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G01R31/318533 , G11C29/56008 , G11C2029/5604
摘要： A system and method for defect analysis are disclosed wherein a defect data set is input into the system. A radius value is selected by a user, which is the maximum number of bits that bit failures can be separated from one another to be considered a bit cluster. When a defect data set is received, the system and method start with a fail bit and search for neighboring fail bits. The specified radius is used to qualify the found fail bits to be part of the bit cluster or not. If a minimum count of fail bits is not met, the system and method will stop searching and move to the next fail bit. If a minimum count of fail bits is met, the search continues for the next fail bit until the maximum fail bit count specified by the user is reached. Aggregation is provided such that once bit clusters have been classified, the number of clusters that have the exact match or partial match to each other is counted. The user may set the partial match as a threshold count to establish a match.
摘要翻译：公开了一种用于缺陷分析的系统和方法，其中缺陷数据集被输入到系统中。半径值由用户选择，这是位故障可以彼此分离以被认为是位簇的最大位数。当接收到缺陷数据集时，系统和方法以故障位开始，并搜索相邻的故障位。指定的半径用于将找到的故障位限定为位集群的一部分。如果不满足最小失败位计数，系统和方法将停止搜索并移动到下一个故障位。如果满足最小失败位计数，则搜索继续下一个故障位，直到达到用户指定的最大故障位数。提供聚合，使得一旦对位簇进行分类，就会计算出具有完全匹配或彼此部分匹配的聚类的数量。用户可以将部分匹配设置为阈值计数以建立匹配。

3. 发明授权

US07685481B2 Bitmap cluster analysis of defects in integrated circuits 有权
标题翻译：集成电路缺陷位图聚类分析
公开(公告)号：US07685481B2
公开(公告)日：2010-03-23
申请号：US11166960
申请日：2005-06-23
申请人： Tom T. Ho , Jonathan B. Buckheit , Weidong Wang , Xin Sun
发明人： Tom T. Ho , Jonathan B. Buckheit , Weidong Wang , Xin Sun
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G01R31/318533 , G11C29/56008 , G11C2029/5604
摘要： A system and method for defect analysis are disclosed wherein a defect data set is input into the system. A radius value is selected by a user, which is the maximum number of bits that bit failures can be separated from one another to be considered a bit cluster. When a defect data set is received, the system and method start with a fail bit and search for neighboring fail bits. The specified radius is used to qualify the found fail bits to be part of the bit cluster or not. If a minimum count of fail bits is not met, the system and method will stop searching and move to the next fail bit. If a minimum count of fail bits is met, the search continues for the next fail bit until the maximum fail bit count specified by the user is reached. Aggregation is provided such that once bit clusters have been classified, the number of clusters that have the exact match or partial match to each other is counted. The user may set the partial match as a threshold count to establish a match.
摘要翻译：公开了一种用于缺陷分析的系统和方法，其中缺陷数据集被输入到系统中。半径值由用户选择，这是位故障可以彼此分离以被认为是位簇的最大位数。当接收到缺陷数据集时，系统和方法以故障位开始，并搜索相邻的故障位。指定的半径用于将找到的故障位限定为位集群的一部分。如果不满足最小失败位计数，系统和方法将停止搜索并移动到下一个故障位。如果满足最小失败位计数，则搜索继续下一个故障位，直到达到用户指定的最大故障位数。提供聚合，使得一旦对位簇进行分类，就会计算出具有完全匹配或彼此部分匹配的聚类的数量。用户可以将部分匹配设置为阈值计数以建立匹配。

4. 发明申请

US20100235690A1 BITMAP CLUSTER ANALYSIS OF DEFECTS IN INTEGRATED CIRCUITS 有权
标题翻译：综合电路缺陷的BITMAP聚类分析
公开(公告)号：US20100235690A1
公开(公告)日：2010-09-16
申请号：US12728629
申请日：2010-03-22
申请人： Tom T. Ho , Jonathan B. Buckheit , Weidong Wang , Xin Sun
发明人： Tom T. Ho , Jonathan B. Buckheit , Weidong Wang , Xin Sun
IPC分类号： G06F11/00
CPC分类号： G11C29/56 , G01R31/318533 , G11C29/56008 , G11C2029/5604
摘要： A system and method for defect analysis are disclosed wherein a defect data set is input into the system. A radius value is selected by a user, which is the maximum number of bits that bit failures can be separated from one another to be considered a bit cluster. When a defect data set is received, the system and method start with a fail bit and search for neighboring fail bits. The specified radius is used to qualify the found fail bits to be part of the bit cluster or not. If a minimum count of fail bits is not met, the system and method will stop searching and move to the next fail bit. If a minimum count of fail bits is met, the search continues for the next fail bit until the maximum fail bit count specified by the user is reached. Aggregation is provided such that once bit clusters have been classified, the number of clusters that have the exact match or partial match to each other is counted. The user may set the partial match as a threshold count to establish a match.
摘要翻译：公开了一种用于缺陷分析的系统和方法，其中缺陷数据集被输入到系统中。半径值由用户选择，这是位故障可以彼此分离以被认为是位簇的最大位数。当接收到缺陷数据集时，系统和方法以故障位开始，并搜索相邻的故障位。指定的半径用于将找到的故障位限定为位集群的一部分。如果不满足最小失败位计数，系统和方法将停止搜索并移动到下一个故障位。如果满足最小失败位计数，则搜索继续下一个故障位，直到达到用户指定的最大故障位数。提供聚合，使得一旦对位簇进行分类，就会计算出具有完全匹配或彼此部分匹配的聚类的数量。用户可以将部分匹配设置为阈值计数以建立匹配。

5. 发明申请

US20080189582A1 Analysis techniques for multi-level memory 有权
标题翻译：多级内存分析技术
公开(公告)号：US20080189582A1
公开(公告)日：2008-08-07
申请号：US11701700
申请日：2007-02-02
申请人： Tom T. Ho , Jonathan B. Buckheit , Weldong Wang
发明人： Tom T. Ho , Jonathan B. Buckheit , Weldong Wang
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C29/10 , G11C29/56008
摘要： A system and method for defect analysis of multi-level memory cell devices and embedded multi-level memory in system-on-chip integrated circuits are disclosed wherein a defect data set is input into the system. When a defect data set is received, an automated test engineering system running a memory test program analyzes the defect data set to generate one or more fail bit locations and one or more fail states of the memory. The multi-level memory defect analysis system and method then classify failed bits or patterns comprising a vertical fail pattern, whereby after being classified, each memory cell failure vertical fail pattern has three data attributes comprising fail type, a number of fail bits/states, and a sequence of the fail states. The vertical fail pattern may comprise a single fail state or multi-state fail. The multi-state fail may be a continuous-states fail, discontinuous-states fail, or all-state fail. The multi-level memory defect analysis system and method may additionally enable classification of failed bits or patterns comprising a lateral fail pattern. The lateral fail pattern may be a gradual fail pattern, periodic fail pattern, or random fail pattern.
摘要翻译：公开了一种用于系统级芯片集成电路中的多级存储单元器件和嵌入式多级存储器的缺陷分析的系统和方法，其中将缺陷数据集输入到系统中。当接收到缺陷数据集时，运行内存测试程序的自动测试工程系统分析缺陷数据集以生成一个或多个故障位位置和存储器的一个或多个故障状态。多级存储器缺陷分析系统和方法然后对包括垂直故障模式的故障位或模式进行分类，由此在分类之后，每个存储单元故障垂直故障模式具有包括故障类型，多个故障位/状态的三个数据属性，和一系列的失败状态。垂直故障模式可能包含单个故障状态或多状态故障。多状态失败可能是连续状态失败，不连续状态失败或全状态失败。多级存储器缺陷分析系统和方法还可以使得能够对包括横向失效模式的故障位或模式进行分类。横向失效模式可能是逐渐失败模式，周期性失败模式或随机失败模式。

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