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1. 发明授权

US07395470B2 Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chain 失效
公开(公告)号：US07395470B2
公开(公告)日：2008-07-01
申请号：US11149483
申请日：2005-06-09
申请人： Todd M. Burdine , Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Phong T. Tran
发明人： Todd M. Burdine , Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Phong T. Tran
IPC分类号： G01R31/28
CPC分类号： G06F11/2215
摘要： A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.

2. 发明授权

US07392449B2 Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chain 失效
标题翻译：用于使用耦合到扫描链的保险丝诊断扫描链故障的方法，装置和计算机程序产品
公开(公告)号：US07392449B2
公开(公告)日：2008-06-24
申请号：US11956480
申请日：2007-12-14
申请人： Todd M. Burdine , Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Phong T. Tran
发明人： Todd M. Burdine , Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Phong T. Tran
IPC分类号： G01R31/28
CPC分类号： G06F11/2215
摘要： A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.
摘要翻译：提供了实现扫描链诊断技术的方法，装置和计算机程序产品。诊断技术包括使用耦合到扫描链的锁存器的熔丝将已知逻辑值加载到扫描链的已知位置处的锁存器中，然后从扫描链中卸载值，并且如果扫描链有缺陷（例如，基于卸载的逻辑值），然后通过与已加载逻辑值的扫描链中的缺陷通过经由保险丝加载了已知逻辑值的扫描链的锁存器的已知位置进行比较来定位扫描链中的缺陷。可以使用每n个锁存器在链上周期性间隔的保险丝对扫描链进行预先设计，以便于扫描链中检测到的缺陷的随后定位。

3. 发明授权

US07340496B2 System and method for determining the Nth state of linear feedback shift registers 有权
标题翻译：用于确定线性反馈移位寄存器的第N状态的系统和方法
公开(公告)号：US07340496B2
公开(公告)日：2008-03-04
申请号：US10707481
申请日：2003-12-17
申请人： Todd M. Burdine , Edward E. Kelley , Franco Motika
发明人： Todd M. Burdine , Edward E. Kelley , Franco Motika
IPC分类号： G06F1/02
CPC分类号： G06F7/584 , G06F2207/582
摘要： The Nth state of an n-stage linear feedback shift register (LFSR) used to generate pseudo random binary sequences or patterns, and which may be configured as a multiple input signature register (MISR) or single input signature register (SISR) to compress data and generate signatures, is determined by building a look-up table of n-bit states for latch positions of the linear feedback shift register; obtaining the modulo remainder of the Nth state; and generating the Nth state directly from the modulo remainder and n-bit states.
摘要翻译：用于产生伪随机二进制序列或模式的n级线性反馈移位寄存器（LFSR）的第N状态，并且其可被配置为多输入签名寄存器（MISR）或单输入签名寄存器（SISR）以压缩数据并通过建立线性反馈移位寄存器的锁存位置的n位状态的查找表来确定生成签名; 获得第N个状态的模余数; 并且从模余数和n位状态直接产生第N状态。

4. 发明授权

US07234090B2 Method and apparatus for selective scan chain diagnostics 有权
标题翻译：用于选择性扫描链诊断的方法和装置
公开(公告)号：US07234090B2
公开(公告)日：2007-06-19
申请号：US10932607
申请日：2004-09-02
申请人： Charles J. Blasi , Todd M. Burdine , Orazio P. Forlenza
发明人： Charles J. Blasi , Todd M. Burdine , Orazio P. Forlenza
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/318569 , G01R31/318536
摘要： A method, apparatus and program product for testing at least one scan chain in an electronic chip in which the scan chain is formed by shift register latches arranged in the chain having a scan path with input pins and output pins. A flush test is executed for the scan chain under test and the flush test diagnostics for the flush test are recorded. A scan test is then executed for the scan chain under test and further test diagnostics are recorded in the event either or both the flush test or the scan test fails. The recorded flush test diagnostics and further test diagnostics are then analyzed to identify a call to one or more probable failed or failing shift register latches in the tested scan chain. The further scan chain diagnostics may include Disturb, Deterministic, ABIST, LBIST and Look-Ahead diagnostics. The tests may also be conducted for different voltage levels to determine the sensitivity of the scan chain being tested to differing voltage levels.
摘要翻译：一种用于测试电子芯片中的至少一个扫描链的方法，装置和程序产品，其中扫描链由布置在链中的移位寄存器锁存器形成，其具有带有输入引脚和输出引脚的扫描路径。对被测扫描链执行冲洗测试，并记录冲洗测试的冲洗测试诊断。然后对被测试的扫描链执行扫描测试，并且在冲洗测试或扫描测试失败的情况下记录进一步的测试诊断。然后分析记录的冲洗测试诊断和进一步的测试诊断，以识别对被测扫描链中的一个或多个可能的故障或失败的移位寄存器锁存器的呼叫。进一步的扫描链诊断可以包括打扰，确定性，ABIST，LBIST和前瞻诊断。还可以对不同的电压电平进行测试，以确定被测试的扫描链的灵敏度不同于电压水平。

5. 发明授权

US07089474B2 Method and system for providing interactive testing of integrated circuits 失效
标题翻译：提供集成电路交互式测试的方法和系统
公开(公告)号：US07089474B2
公开(公告)日：2006-08-08
申请号：US10789710
申请日：2004-02-27
申请人： Todd M. Burdine , Franco Motika , Peilin Song
发明人： Todd M. Burdine , Franco Motika , Peilin Song
IPC分类号： G06F11/00 , G06F17/50
CPC分类号： G06F11/261 , G01R31/31703 , G01R31/318371 , G06F11/263
摘要： A method for providing interactive and iterative testing of integrated circuits including the receiving of a first failing region. The first failing region corresponds to one or more circuits on the integrated circuit. The method generates a set of adaptive algorithmic test patterns for the one or more circuits in response to the first failing region and to a logic model of the integrated circuit. Expected results for the test patterns are determined. The method includes applying the test patterns to the first failing region on the integrated circuit resulting in actual results for the test patterns. The expected results to the actual results are compared. The method also transmits mismatches between the expected results and the actual results to a fault simulator. The method includes receiving a second failing region from the fault simulator, the second failing region created in response to the mismatches and the logic model, and the second failing region corresponding to a subset of the one or more circuits on the integrated circuit.
摘要翻译：一种用于提供集成电路的交互式和迭代测试的方法，包括接收第一故障区域。第一故障区域对应于集成电路上的一个或多个电路。该方法响应于第一故障区域和集成电路的逻辑模型生成针对一个或多个电路的一组自适应算法测试模式。确定测试模式的预期结果。该方法包括将测试图案应用于集成电路上的第一故障区域，从而得到测试图案的实际结果。对实际结果的预期结果进行比较。该方法还将预期结果与实际结果之间的错配传输到故障模拟器。该方法包括从故障模拟器接收第二故障区域，响应于不匹配和逻辑模型而创建的第二故障区域，以及对应于集成电路上的一个或多个电路的子集的第二故障区域。

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