专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06650015B2 Cavity-down ball grid array package with semiconductor chip solder ball 有权
标题翻译：具有半导体芯片焊球的凹陷球栅阵列封装
公开(公告)号：US06650015B2
公开(公告)日：2003-11-18
申请号：US10173213
申请日：2002-06-14
申请人： Eing-Chieh Chen , Shiu-Tai Tzung , Ting-Ke Chai , Jeng-Yuan Lai , Candy Tien
发明人： Eing-Chieh Chen , Shiu-Tai Tzung , Ting-Ke Chai , Jeng-Yuan Lai , Candy Tien
IPC分类号： H01L2348
CPC分类号： H01L24/73 , H01L23/13 , H01L23/3128 , H01L23/36 , H01L24/17 , H01L24/48 , H01L24/49 , H01L24/91 , H01L2224/05554 , H01L2224/13099 , H01L2224/16 , H01L2224/48095 , H01L2224/48227 , H01L2224/49171 , H01L2224/73207 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A cavity-down ball grid array package includes a substrate having a through cavity provided therein. A heat sink is attached to the substrate and a semiconductor chip in the cavity is attached to the heat sink and electrically connected to the substrate. A ball grid array is on the substrate and on the semiconductor chip.
摘要翻译：空腔向下的球栅阵列封装包括其中设置有通孔的衬底。将散热器附接到基板，并且空腔中的半导体芯片附接到散热器并电连接至基板。球栅阵列位于衬底和半导体芯片上。

2. 发明授权

US06555924B2 Semiconductor package with flash preventing mechanism and fabrication method thereof 有权
标题翻译：具有防闪光机构的半导体封装及其制造方法
公开(公告)号：US06555924B2
公开(公告)日：2003-04-29
申请号：US09932054
申请日：2001-08-18
申请人： Ting Ke Chai , Po Hauu Yuan , Han Ping Pu
发明人： Ting Ke Chai , Po Hauu Yuan , Han Ping Pu
IPC分类号： H01L2329
CPC分类号： B29C45/34 , H01L21/565 , H01L23/564 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/14 , H01L2924/15311 , H01L2924/1815 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor package and a fabricating method thereof are proposed, in which a substrate is prepared for having at least one flash preventing mechanism disposed on a surface of the substrate corresponding to a position in front of an entry of an air vent in a mold. After a semiconductor chip is mounted on the substrate by a plurality of conductive elements, a molding compound having high fluidity and fine filler particles is used to encapsulate the chip and the flash preventing mechanism. As the flash preventing mechanism is disposed in a manner of reducing the entry space of the air vent, the flow of the molding compound is impeded by the flash preventing mechanism, making the molding compound rapidly absorb heat of the mold and accordingly increased in viscosity. This helps prevent flash of the molding compound from occurrence, and assure the semiconductor package in quality and profile.
摘要翻译：提出了一种半导体封装及其制造方法，其中制备了具有至少一个防闪除机构的衬底，其布置在与模具中的通风口的入口前方的位置对应的衬底的表面上。在通过多个导电元件将半导体芯片安装在基板上之后，使用具有高流动性的模塑料和细填料颗粒来封装芯片和闪光防止机构。由于防闪发机构以减少排气口的进入空间的方式设置，所以模塑料的流动被防闪光机构阻碍，使得模塑料快速吸收模具的热量并因此提高了粘度。这有助于防止模塑料的闪光发生，并确保半导体封装的质量和外形。

3. 发明授权

US06359342B1 Flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same 有权
标题翻译：在半导体芯片上具有专用测试焊盘的倒装凸块结构及其制造方法
公开(公告)号：US06359342B1
公开(公告)日：2002-03-19
申请号：US09730311
申请日：2000-12-05
申请人： Pao-Ho Yuan , Ting-Ke Chai , Lien-Chi Chan , Jen-Yi Tsai
发明人： Pao-Ho Yuan , Ting-Ke Chai , Lien-Chi Chan , Jen-Yi Tsai
IPC分类号： H01L2348
CPC分类号： H01L22/32 , H01L22/20 , H01L23/50 , H01L24/11 , H01L2224/0401 , H01L2224/05554 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/014 , H01L2924/14 , H01L2924/00014
摘要： A flip-chip bumping technology is proposed, which provides a flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same. The proposed flip-chip bumping technology is characterized by the forming of a lined-array of electrically-conductive dual-pad blocks respectively over the internal I/O points of the semiconductor chip, each dual-pad block including a first pad and a second pad located beside and electrically connected to the first pad; and wherein the respective first and second pads of the dual-pad blocks-are alternately designated as bump pads and test pads. During testing procedure, the probing to the internal circuitry of the semiconductor chip is carried out through the test-pad portions of the dual-pad blocks, so that the probing needles would leave no scratches over the bumppad portions of the same. During subsequent bumping process, solder bumps are formed respectively over the bump-pad portions of the dual-pad blocks. Since the bump-pad portions of the dual-pad blocks would be left unscratched, it allows the solder bump attachment to be more assured in quality and reliability.
摘要翻译：提出了一种倒装芯片凸块技术，其提供了具有半导体芯片上的专用测试焊盘的倒装芯片凸块结构及其制造方法。所提出的倒装芯片凸块技术的特征在于分别在半导体芯片的内部I / O点上形成导电双焊盘块的排列阵列，每个双焊盘块包括第一焊盘和第二焊盘垫位于旁边并电连接到第一垫; 并且其中所述双焊盘块的相应的第一和第二焊盘被交替地指定为凸块焊盘和测试焊盘。在测试过程中，半导体芯片的内部电路的探测通过双焊盘块的测试焊盘部分进行，使得探针不会在其上的焊盘部分上留下划痕。在随后的凸块处理期间，分别在双焊盘块的凸块焊盘部分上形成焊料凸块。由于双焊盘块的凸块焊盘部分将不被打开，所以允许焊料凸块附着在质量和可靠性方面更加确保。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式