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1. 发明授权

US07199616B2 Method and apparatus to generate break before make signals for high speed TTL driver 有权
标题翻译：在高速TTL驱动器产生信号之前产生中断的方法和装置
公开(公告)号：US07199616B2
公开(公告)日：2007-04-03
申请号：US11000468
申请日：2004-11-29
申请人： Timothy Lu
发明人： Timothy Lu
IPC分类号： H03K19/094 , H03H11/26
CPC分类号： H03K5/1515 , H03K5/133
摘要： A driver includes, in part, a delay chain having disposed therein a multitude of accessible nodes, and a control logic coupled to the various nodes of the delay chain to generate the signals applied to the gate terminals of the PMOS and NMOS transistors disposed in the driver. The nodes that are accessed and tapped may or may not be the successive nodes disposed along the delay chain. Optionally four nodes of the delay chain are tapped to supply signals to the control logic. Two of the nodes, carrying in-phase signals, are tapped to generate a first signal, which is used to generate a second signal driving the NMOS transistor. The other two nodes, carrying in-phase signals, are tapped to generate a third signal, which is used to generate a fourth signal driving the PMOS transistor. The first signal is 180° out-of-phase with respect to the third signal.
摘要翻译：驱动器部分地包括其中设置有多个可访问节点的延迟链，以及耦合到延迟链的各个节点的控制逻辑，以产生施加到PMOS和NMOS晶体管的栅极端子的信号司机。被访问和点击的节点可以是或可以不是沿延迟链设置的连续节点。可选地，延迟链的四个节点被抽头以向控制逻辑提供信号。带有同相信号的节点中的两个被抽头以产生第一信号，其用于产生驱动NMOS晶体管的第二信号。带有同相信号的另外两个节点被抽头以产生用于产生驱动PMOS晶体管的第四信号的第三信号。第一信号相对于第三信号是异相180°。

2. 发明申请

US20060114028A1 Method and apparatus to generate break before make signals for high speed TTL driver 有权
标题翻译：在高速TTL驱动器产生信号之前产生中断的方法和装置
公开(公告)号：US20060114028A1
公开(公告)日：2006-06-01
申请号：US11000468
申请日：2004-11-29
申请人： Timothy Lu
发明人： Timothy Lu
IPC分类号： H03K19/094
CPC分类号： H03K5/1515 , H03K5/133
摘要： A driver includes, in part, a delay chain having disposed therein a multitude of accessible nodes, and a control logic coupled to the various nodes of the delay chain to generate the signals applied to the gate terminals of the PMOS and NMOS transistors disposed in the driver. The nodes that are accessed and tapped may or may not be the successive nodes disposed along the delay chain. Optionally four nodes of the delay chain are tapped to supply signals to the control logic. Two of the nodes, carrying in-phase signals, are tapped to generate a first signal, which is used to generate a second signal driving the NMOS transistor. The other two nodes, carrying in-phase signals, are tapped to generate a third signal, which is used to generate a fourth signal driving the PMOS transistor. The first signal is 180° out-of-phase with respect to the third signal.
摘要翻译：驱动器部分地包括其中设置有多个可访问节点的延迟链，以及耦合到延迟链的各个节点的控制逻辑，以产生施加到设置在所述延迟链中的PMOS和NMOS晶体管的栅极端子的信号司机。被访问和点击的节点可以是或可以不是沿延迟链设置的连续节点。可选地，延迟链的四个节点被抽头以向控制逻辑提供信号。带有同相信号的节点中的两个被抽头以产生第一信号，其用于产生驱动NMOS晶体管的第二信号。带有同相信号的另外两个节点被抽头以产生第三信号，其用于产生驱动PMOS晶体管的第四信号。第一信号相对于第三信号是异相180°。

3. 发明授权

US07091754B2 CMOS LvPECL driver with output level control 失效
标题翻译： CMOS LvPECL驱动器，具有输出电平控制
公开(公告)号：US07091754B2
公开(公告)日：2006-08-15
申请号：US10879475
申请日：2004-06-28
申请人： Timothy Lu , Vincent S. Tso
发明人： Timothy Lu , Vincent S. Tso
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , H03K5/2481
摘要： A differential output driver includes an output block, a replication block, and a feedback control block. Each of the output and replication blocks further includes a preamplifier and a source-follower stage. The preamplifier of the output block receives a differential input voltage and generates a first differential voltage. The source-follower stage of the output block receives the first differential voltage and generates a differential output voltage. The preamplifier of the replication block receives first and second supply voltages and generates a second differential voltage. The source-follower stage of the output block receives the second differential voltage and generates a third differential voltage. The feedback control block receives the third differential voltage and generates a differential control voltage applied to the output block. The generated differential output voltage stays within predefined limits, such as those defined by the LvPECL standard.
摘要翻译：差分输出驱动器包括输出块，复制块和反馈控制块。每个输出和复制块还包括前置放大器和源极跟随器级。输出块的前置放大器接收差分输入电压并产生第一差分电压。输出块的源极跟随器级接收第一差分电压并产生差分输出电压。复制块的前置放大器接收第一和第二电源电压并产生第二差分电压。输出块的源极跟随器级接收第二差分电压并产生第三差分电压。反馈控制块接收第三差分电压并产生施加到输出块的差分控制电压。产生的差分输出电压保持在预定义的限制内，例如由LvPECL标准定义的限制。

4. 发明授权

US08645115B2 Modular nucleic acid-based circuits for counters, binary operations, memory and logic 有权
标题翻译：用于计数器，二进制操作，存储器和逻辑的基于模块化的基于核酸的电路
公开(公告)号：US08645115B2
公开(公告)日：2014-02-04
申请号：US13141165
申请日：2009-12-22
申请人： James J Collins , Timothy Lu
发明人： James J Collins , Timothy Lu
IPC分类号： G06G7/48 , G06G7/58 , G01N33/48 , G01N31/00
CPC分类号： C12Q1/6897 , C12N15/63 , C12N15/635 , C12Q2521/507
摘要： We have created novel engineered genetic counter designs and methods of use thereof that utilize DNA recombinases to provide modular systems, termed single invertase memory modules (SIMMs), for encoding memory in cells and cellular systems. Our designs are easily extended to compute to high numbers, by utilizing the >100 known recombinases to create subsequent modules. Flexibility in our engineered genetic counter designs is provided by daisy-chaining individual modular components, i.e., SIMMs together. These modular components of the engineered genetic counters can be combined in other network topologies to create circuits that perform, amongst other things, logic and memory. Our novel engineered genetic counter designs allow for the maintenance of memory and provide the ability to count between discrete states by expressing the recombinases between their cognate recognition sites.
摘要翻译：我们已经创建了新颖的遗传算法设计及其使用方法，其利用DNA重组酶来提供称为单一转换酶存储器模块（SIMM）的模块化系统，用于对细胞和细胞系统中的存储器进行编码。通过使用> 100个已知重组酶来创建后续模块，我们的设计可以轻松扩展到高数量计算。我们设计的基因计数器设计中的灵活性是通过菊花链连接单个模块化组件（即SIMM）来提供的。设计的遗传计数器的这些模块化组件可以组合在其他网络拓扑中，以创建执行逻辑和存储器的电路。我们的新颖设计的基因计数器设计允许维持记忆，并提供通过在其同源识别位点之间表达重组酶来提供离散状态之间的计数能力。

5. 发明授权

US07330056B1 Low power CMOS LVDS driver 有权
标题翻译：低功耗CMOS LVDS驱动器
公开(公告)号：US07330056B1
公开(公告)日：2008-02-12
申请号：US11296187
申请日：2005-12-06
申请人： Timothy Lu
发明人： Timothy Lu
IPC分类号： H03K3/00
CPC分类号： H04L25/028
摘要： A low voltage CMOS output driver is adapted to generate an output voltage that stays within predefined limits at relatively low supply voltages. The output driver includes, in part, a voltage-controlled resistor, a voltage-controlled current sink, and a switching stage. A control circuit provides the voltages that are applied to the voltage-controlled resistor and the voltage-controlled current sink. The voltage applied to the voltage-controlled resistor defines the high output voltage. The voltage applied to the voltage-controlled current sink defines the low output voltage. The control circuit is a scaled replica of the output driver and is adapted to consume a current that is 1/L times the current consumed by the output driver.
摘要翻译：低电压CMOS输出驱动器适于产生在相对低的电源电压下保持在预定义限度内的输出电压。输出驱动器部分地包括压控电阻器，压控电流吸收器和开关级。控制电路提供施加到压控电阻器和压控电流吸收器的电压。施加到压控电阻器的电压定义了高输出电压。施加到压控电流吸收器的电压定义了低输出电压。控制电路是输出驱动器的缩放副本，并且适于消耗电流，其是输出驱动器消耗的电流的1 / L倍。

6. 发明申请

US20120003630A1 MODULAR NUCLEIC ACID-BASED CIRCUITS FOR COUNTERS, BINARY OPERATIONS, MEMORY, AND LOGIC 有权
标题翻译：用于计数器，二进制运算，存储器和逻辑的基于核酸的基于电路的电路
公开(公告)号：US20120003630A1
公开(公告)日：2012-01-05
申请号：US13141165
申请日：2009-12-22
申请人： James J. Collins , Timothy Lu
发明人： James J. Collins , Timothy Lu
IPC分类号： C12Q1/68 , C12N15/63
CPC分类号： C12Q1/6897 , C12N15/63 , C12N15/635 , C12Q2521/507
摘要： We have created novel engineered genetic counter designs and methods of use thereof that utilize DNA recombinases to provide modular systems, termed single invertase memory modules (SIMMs), for encoding memory in cells and cellular systems. Our designs are easily extended to compute to high numbers, by utilizing the >100 known recombinases to create subsequent modules. Flexibility in our engineered genetic counter designs is provided by daisy-chaining individual modular components, i.e., SIMMs together. These modular components of the engineered genetic counters can be combined in other network topologies to create circuits that perform, amongst other things, logic and memory. Our novel engineered genetic counter designs allow for the maintenance of memory and provide the ability to count between discrete states by expressing the recombinases between their cognate recognition sites.
摘要翻译：我们已经创建了新颖的遗传算法设计及其使用方法，其利用DNA重组酶来提供称为单一转换酶存储器模块（SIMM）的模块化系统，用于对细胞和细胞系统中的存储器进行编码。通过使用> 100个已知重组酶来创建后续模块，我们的设计可以轻松扩展到高数量计算。我们设计的基因计数器设计中的灵活性是通过菊花链连接单个模块化组件（即SIMM）来提供的。设计的遗传计数器的这些模块化组件可以组合在其他网络拓扑中，以创建执行逻辑和存储器的电路。我们的新颖设计的基因计数器设计允许维持记忆，并提供通过在其同源识别位点之间表达重组酶来提供离散状态之间的计数能力。

7. 发明申请

US20050285637A1 CMOS LvPECL driver with output level control 失效
标题翻译： CMOS LvPECL驱动器，具有输出电平控制
公开(公告)号：US20050285637A1
公开(公告)日：2005-12-29
申请号：US10879475
申请日：2004-06-28
申请人： Timothy Lu , Vincent Tso
发明人： Timothy Lu , Vincent Tso
IPC分类号： H03B1/00 , H03K5/24 , H03K19/0185
CPC分类号： H03K19/018528 , H03K5/2481
摘要： A differential output driver includes an output block, a replication block, and a feedback control block. Each of the output and replication blocks further includes a preamplifier and a source-follower stage. The preamplifier of the output block receives a differential input voltage and generates a first differential voltage. The source-follower stage of the output block receives the first differential voltage and generates a differential output voltage. The preamplifier of the replication block receives first and second supply voltages and generates a second differential voltage. The source-follower stage of the output block receives the second differential voltage and generates a third differential voltage. The feedback control block receives the third differential voltage and generates a differential control voltage applied to the output block. The generated differential output voltage stays within predefined limits, such as those defined by the LvPECL standard.
摘要翻译：差分输出驱动器包括输出块，复制块和反馈控制块。每个输出和复制块还包括前置放大器和源极跟随器级。输出块的前置放大器接收差分输入电压并产生第一差分电压。输出块的源极跟随器级接收第一差分电压并产生差分输出电压。复制块的前置放大器接收第一和第二电源电压并产生第二差分电压。输出块的源极跟随器级接收第二差分电压并产生第三差分电压。反馈控制块接收第三差分电压并产生施加到输出块的差分控制电压。产生的差分输出电压保持在预定义的限制内，例如由LvPECL标准定义的限制。

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