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1. 发明授权

US07536517B2 Direct-update software transactional memory 有权
标题翻译：直接更新软件事务内存
公开(公告)号：US07536517B2
公开(公告)日：2009-05-19
申请号：US11192784
申请日：2005-07-29
申请人： Timothy L. Harris
发明人： Timothy L. Harris
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F17/30
CPC分类号： G06F9/467 , Y10S707/99938 , Y10S707/99939
摘要： A transactional memory programming interface allows a thread to directly and safely access one or more shared memory locations within a transaction while maintaining control structures to manage memory accesses to those same locations by one or more other concurrent threads. Each memory location accessed by the thread is associated with an enlistment record, and each thread maintains a transaction log of its memory accesses. Within a transaction, a read operation is performed directly on the memory location, and a write operation is attempted directly on the memory location, as opposed to some intermediate buffer. The thread can detect inconsistencies between the enlistment record of a memory location and the thread's transaction log to determine whether the memory accesses within the transaction are not reliable and the transaction should be re-tried.
摘要翻译：事务存储器编程接口允许线程直接和安全地访问事务内的一个或多个共享存储器位置，同时维护控制结构以通过一个或多个其他并发线程来管理对那些相同位置的存储器访问。由线程访问的每个内存位置都与一个登记记录相关联，每个线程都维护其内存访问的事务日志。在事务中，直接对存储器位置执行读取操作，并且与一些中间缓冲器相反，直接在存储器位置上进行写入操作。线程可以检测内存位置的登记记录与线程的事务日志之间的不一致，以确定事务中的内存访问是否不可靠，并且应重新尝试该事务。

2. 发明授权

US07117502B1 Linked-list implementation of a data structure with concurrent non-blocking insert and remove operations 有权
标题翻译：链接列表实现具有并发的非阻塞插入和删除操作的数据结构
公开(公告)号：US07117502B1
公开(公告)日：2006-10-03
申请号：US09710218
申请日：2000-11-10
申请人： Timothy L. Harris
发明人： Timothy L. Harris
IPC分类号： G06F9/54
CPC分类号： G06F9/524 , Y10S707/99944
摘要： A simple and therefore highly usable non-blocking implementations of linked-lists can be provided using read, write, and CAS operations. Several realizations of linked-list based data-structures are described, which are non-blocking, linearizable, and exhibit disjoint-access for most operations. In other words, the realizations are non-blocking and linearizable while maintaining the property that operations on disjoint parts of the list do not interact, effectively lowering contention and increasing concurrency. We implement three exemplary data structures: sets, multi-sets, and ordered-sets. The exemplary implementations support insert, remove, and find operations, with natural semantics. An ordered-set implementation supports an additional removeGE operation.
摘要翻译：可以使用读取，写入和CAS操作来提供链接列表的简单且因此高度可用的非阻塞实现。描述了基于链表的数据结构的几种实现，对于大多数操作，它们是非阻塞的，可线性化的，并且表现出不相交的访问。换句话说，实现是非阻塞和线性化的，同时保持列表不相交部分的操作不相互作用，有效降低争用并增加并发性的属性。我们实现了三个典型的数据结构：集合，多集和有序集。示例性实现支持使用自然语义插入，删除和查找操作。有序集实现支持额外的removeGE操作。

3. 发明授权

US08225297B2 Cache metadata identifiers for isolation and sharing 有权
标题翻译：缓存用于隔离和共享的元数据标识符
公开(公告)号：US08225297B2
公开(公告)日：2012-07-17
申请号：US11890448
申请日：2007-08-06
申请人： Jan Gray , Timothy L. Harris , James Larus , Burton Smith
发明人： Jan Gray , Timothy L. Harris , James Larus , Burton Smith
IPC分类号： G06F12/00
CPC分类号： G06F12/084
摘要： Various technologies and techniques are disclosed for providing software accessible metadata on a cache of a central processing unit. A multiprocessor has at least one central processing unit. The central processing unit has a cache with cache lines that are augmented by cache metadata. The cache metadata includes software-controlled metadata identifiers that allow multiple logical processors to share the cache metadata. The metadata identifiers and cache metadata can then be used to accelerate various operations. For example, parallel computations can be accelerated using cache metadata and metadata identifiers. As another example, nested computations can be accelerated using metadata identifiers and cache metadata. As yet another example, transactional memory applications that include parallelism within transactions or that include nested transactions can be also accelerated using cache metadata and metadata identifiers.
摘要翻译：公开了用于在中央处理单元的高速缓存上提供软件可访问元数据的各种技术和技术。多处理器具有至少一个中央处理单元。中央处理单元具有高速缓存，缓存线通过高速缓存元数据增强。高速缓存元数据包括允许多个逻辑处理器共享缓存元数据的软件控制的元数据标识符。然后可以使用元数据标识符和缓存元数据来加速各种操作。例如，可以使用缓存元数据和元数据标识符来加速并行计算。作为另一个例子，可以使用元数据标识符和缓存元数据来加速嵌套计算。作为又一示例，还可以使用高速缓存元数据和元数据标识符来加速包括事务内并行性或包括嵌套事务的事务性存储器应用。

4. 发明授权

US08001538B2 Software accessible cache metadata 有权
标题翻译：软件可访问缓存元数据
公开(公告)号：US08001538B2
公开(公告)日：2011-08-16
申请号：US11811148
申请日：2007-06-08
申请人： Jan Gray , Timothy L. Harris , James Larus , Burton Smith
发明人： Jan Gray , Timothy L. Harris , James Larus , Burton Smith
IPC分类号： G06F12/00
CPC分类号： G06F12/0802 , G06F9/30021 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/30181 , G06F9/3802 , G06F9/3834 , G06F12/0842
摘要： Various technologies and techniques are disclosed for providing software accessible metadata on a cache of a central processing unit. The metadata can include at least some bits for each virtual address, at least some bits for each cache line, and at least some bits for the cache overall. An instruction set architecture on the central processing unit is provided that includes additional instructions for interacting with the metadata. New side effects that are introduced into an operation of the central processing unit by a presence of the metadata and the additional instructions. The metadata can be accessed by at least one software program to facilitate an operation of the software program.
摘要翻译：公开了用于在中央处理单元的高速缓存上提供软件可访问元数据的各种技术和技术。元数据可以包括用于每个虚拟地址的至少一些比特，每个高速缓存行的至少一些比特，以及总体上的至少一些比特。提供了中央处理单元上的指令集架构，其包括与元数据交互的附加指令。通过存在元数据和附加指令将新的副作用引入到中央处理单元的操作中。元数据可以由至少一个软件程序访问以便于软件程序的操作。

5. 发明申请

US20100211931A1 STM WITH GLOBAL VERSION OVERFLOW HANDLING 有权
标题翻译： STM与全球版本的超流量处理
公开(公告)号：US20100211931A1
公开(公告)日：2010-08-19
申请号：US12370742
申请日：2009-02-13
申请人： Yosseff Levanoni , David L. Detlefs , Weirong Zhu , Timothy L. Harris , Michael M. Magruder , Mathew B. Tolton
发明人： Yosseff Levanoni , David L. Detlefs , Weirong Zhu , Timothy L. Harris , Michael M. Magruder , Mathew B. Tolton
IPC分类号： G06F9/44
CPC分类号： G06F9/466 , G06F11/141
摘要： A software transactional memory system is provided with overflow handling. The system includes a global version counter with an epoch number and a version number. The system accesses the global version counter prior to and subsequent to memory accesses of transactions to validate read accesses of the transaction. The system includes mechanisms to detect global version number overflow and may allow some or all transactions to execute to completion subsequent to the global version number overflowing. The system also provides publication, privatization, and granular safety properties.
摘要翻译：软件事务内存系统提供溢出处理。该系统包括具有时代号和版本号的全局版本计数器。系统在事务的内存访问之前和之后访问全局版本计数器，以验证事务的读取访问。该系统包括检测全局版本号溢出的机制，并且可允许一些或所有事务在全球版本号码溢出之后执行完成。该系统还提供出版物，私有化和粒状安全属性。

6. 发明授权

US08898652B2 Cache metadata for accelerating software transactional memory 有权
标题翻译：缓存用于加速软件事务内存的元数据
公开(公告)号：US08898652B2
公开(公告)日：2014-11-25
申请号：US11811033
申请日：2007-06-08
申请人： Jan Gray , Timothy L. Harris , James Larus , Burton Smith
发明人： Jan Gray , Timothy L. Harris , James Larus , Burton Smith
IPC分类号： G06F9/45 , G06F9/30 , G06F9/46
CPC分类号： G06F9/3004 , G06F9/30003 , G06F9/30087 , G06F9/467
摘要： Various technologies and techniques are disclosed for providing a hardware accelerated software transactional memory application. The software transactional memory application has access to metadata in a cache of a central processing unit that can be used to improve the operation of the STM system. For example, open read barrier filtering is provided that uses an opened-for-read bit that is contained in the metadata to avoid redundant open read processing. Similarly, redundant read log validation can be avoided using the metadata. For example, upon entering commit processing for a particular transaction, a get-evictions instruction in an instruction set architecture of the central processing unit is invoked. A retry operation can be optimized using the metadata. The particular transaction is aborted at a current point and put to sleep. The corresponding cache line metadata in the metadata are marked appropriately to efficiently detect a write by another CPU.
摘要翻译：公开了用于提供硬件加速软件事务性存储器应用的各种技术和技术。软件事务存储器应用程序可以访问可用于改进STM系统的操作的中央处理单元的高速缓存中的元数据。例如，提供了打开的读取屏障过滤，该过滤使用元数据中包含的可读取位来避免冗余的打开读取处理。类似地，可以使用元数据避免冗余读取日志验证。例如，在对特定事务进行提交处理时，调用中央处理单元的指令集架构中的取消指令。可以使用元数据优化重试操作。特定的事务在当前中止，并进入睡眠状态。元数据中相应的缓存行元数据被适当地标记以有效地检测另一CPU的写入。

7. 发明申请

US20090210457A1 TRANSACTIONAL MEMORY WITH DYNAMIC SEPARATION 有权
公开(公告)号：US20090210457A1
公开(公告)日：2009-08-20
申请号：US12033715
申请日：2008-02-19
申请人： Martin Abadi , Andrew D. Birrell , Timothy L. Harris , Michael A. Isard , Johnson Hsieh
发明人： Martin Abadi , Andrew D. Birrell , Timothy L. Harris , Michael A. Isard , Johnson Hsieh
IPC分类号： G06F12/00
CPC分类号： G06F9/466 , G06F8/443
摘要： Strong semantics are provided to programs that are correctly synchronized in their use of transactions by using dynamic separation of objects that are accessed in transactions from those accessed outside transactions. At run-time, operations are performed to identify transitions between these protected and unprotected modes of access. Dynamic separation permits a range of hardware-based and software-based implementations which allow non-conflicting transactions to execute and commit in parallel. A run-time checking tool, analogous to a data-race detector, may be provided to test dynamic separation of transacted data and non-transacted data. Dynamic separation may be used in an asynchronous I/O library.

8. 发明申请

US20090204969A1 TRANSACTIONAL MEMORY WITH DYNAMIC SEPARATION 审中-公开
标题翻译：具有动态分离的交互式存储器
公开(公告)号：US20090204969A1
公开(公告)日：2009-08-13
申请号：US12029130
申请日：2008-02-11
申请人： Martin Abadi , Andrew D. Birrell , Timothy L. Harris , Michael A. Isard , Johnson Ta-Chung Hsieh
发明人： Martin Abadi , Andrew D. Birrell , Timothy L. Harris , Michael A. Isard , Johnson Ta-Chung Hsieh
IPC分类号： G06F9/46
CPC分类号： G06F9/466
摘要： Strong semantics are provided to programs that are correctly synchronized in their use of transactions by using dynamic separation of objects that are accessed in transactions from those accessed outside transactions. At run-time, operations are performed to identify transitions between these protected and unprotected modes of access. Dynamic separation permits a range of hardware-based and software-based implementations which allow non-conflicting transactions to execute and commit in parallel. A run-time checking tool, analogous to a data-race detector, may be provided to test dynamic separation of transacted data and non-transacted data. Dynamic separation may be used in an asynchronous I/O library.
摘要翻译：通过使用在访问外部事务处理的事务中访问的对象的动态分离，为使用事务中正确同步的程序提供了强大的语义。在运行时，执行操作以识别这些受保护和不受保护的访问模式之间的转换。动态分离允许一系列基于硬件和基于软件的实现，允许非冲突事务并行执行和提交。可以提供类似于数据竞争检测器的运行时检查工具来测试事务数据和非事务数据的动态分离。动态分离可用于异步I / O库。

9. 发明授权

US07908265B2 Transactional memory with dynamic separation 有权
标题翻译：具有动态分离的事务记忆
公开(公告)号：US07908265B2
公开(公告)日：2011-03-15
申请号：US12033715
申请日：2008-02-19
申请人： Martin Abadi , Andrew D. Birrell , Timothy L. Harris , Michael A. Isard , Johnson Hsieh
发明人： Martin Abadi , Andrew D. Birrell , Timothy L. Harris , Michael A. Isard , Johnson Hsieh
IPC分类号： G06F17/00
CPC分类号： G06F9/466 , G06F8/443
摘要： Strong semantics are provided to programs that are correctly synchronized in their use of transactions by using dynamic separation of objects that are accessed in transactions from those accessed outside transactions. At run-time, operations are performed to identify transitions between these protected and unprotected modes of access. Dynamic separation permits a range of hardware-based and software-based implementations which allow non-conflicting transactions to execute and commit in parallel. A run-time checking tool, analogous to a data-race detector, may be provided to test dynamic separation of transacted data and non-transacted data. Dynamic separation may be used in an asynchronous I/O library.
摘要翻译：通过使用在访问外部事务处理的事务中访问的对象的动态分离，为使用事务中正确同步的程序提供了强大的语义。在运行时，执行操作以识别这些受保护和不受保护的访问模式之间的转换。动态分离允许一系列基于硬件和基于软件的实现，允许非冲突事务并行执行和提交。可以提供类似于数据竞争检测器的运行时检查工具来测试事务数据和非事务数据的动态分离。动态分离可用于异步I / O库。

10. 发明授权

US08813052B2 Cache metadata for implementing bounded transactional memory 有权
标题翻译：缓存用于实现有界事务内存的元数据
公开(公告)号：US08813052B2
公开(公告)日：2014-08-19
申请号：US11811370
申请日：2007-06-08
申请人： Jan Gray , Timothy L. Harris , James Larus , Burton Smith
发明人： Jan Gray , Timothy L. Harris , James Larus , Burton Smith
IPC分类号： G06F9/45 , G06F9/46
CPC分类号： G06F9/467 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F12/0808 , G06F12/0842 , G06F2212/1016 , G06F2212/466 , G06F2212/507
摘要： Various technologies and techniques are disclosed for providing a bounded transactional memory application that accesses cache metadata in a cache of a central processing unit. When performing a transactional read from the bounded transactional memory application, a cache line metadata transaction-read bit is set. When performing a transactional write from the bounded transactional memory application, a cache line metadata transaction-write bit is set and a conditional store is performed. At commit time, if any lines marked with the transaction-read bit or the transaction-write bit were evicted or invalidated, all speculatively written lines are discarded. The application can also interrogate a cache line metadata eviction summary to determine whether a transaction is doomed and then take an appropriate action.
摘要翻译：公开了各种技术和技术，用于提供访问中央处理单元的高速缓存中的高速缓存元数据的有界事务存储器应用。当从有界事务存储器应用程序执行事务读取时，设置缓存行元数据事务读取位。当从有界事务存储器应用程序执行事务写入时，设置高速缓存行元数据事务写入位并执行条件存储。在提交时，如果任何标有事务读取位或事务写入位的行被驱逐或无效，则所有推测写入的行将被丢弃。应用程序还可以询问高速缓存行元数据驱逐摘要以确定事务是否注定失败，然后采取适当的操作。

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