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1. 发明授权

US5313475A ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme 失效
标题翻译： ECC功能具有独立的高性能部分写入或读/修改/写入和奇偶校验预先接口方案
公开(公告)号：US5313475A
公开(公告)日：1994-05-17
申请号：US785558
申请日：1991-10-31
申请人： Daryl C. Cromer , Gene J. Gaudenzi , Paul C. King , Kevin G. Kramer , Timothy J. Louie
发明人： Daryl C. Cromer , Gene J. Gaudenzi , Paul C. King , Kevin G. Kramer , Timothy J. Louie
IPC分类号： G06F11/10 , G06F12/16 , G06F13/36 , H03M13/00
CPC分类号： G06F11/10 , G06F11/1056
摘要： An error correcting code (ECC) function and a parity interface scheme providing a translation capability between the ECC and parity protocols is implemented for memory systems in personal computers (PCs). The ECC function addresses the problems of interfacing memory with a variety of other components that may communicate in words composed of differing numbers of bytes. A partial write function within an ECC module permits a read/modify/write operation without extra components, at faster speeds and with minimal use of the system bus. An improved parity/ECC protocol interface is implemented by choosing an appropriate ECC code to facilitate parity generation and checking. This is done by selecting a code that contains groupings of data bits corresponding to the desired parity scheme. The ECC XOR trees are modified to allow parity checking and error correction decode simultaneously, thereby eliminating the need for two sets of XOR trees in the interface.
摘要翻译：针对个人计算机（PC）中的存储系统，实施了纠错码（ECC）功能和提供ECC和奇偶校验协议之间的转换能力的奇偶校验接口方案。 ECC功能解决了将存储器与可以以不同字节数组成的单词通信的各种其他组件进行接口的问题。 ECC模块内的部分写入功能允许读取/修改/写入操作，无需额外的组件，速度更快，并且最少使用系统总线。通过选择适当的ECC代码来实现改进的奇偶校验/ ECC协议接口，以便于奇偶校验生成和检查。这通过选择包含对应于所需奇偶校验方案的数据位分组的代码来完成。 ECC XOR树被修改为允许同时进行奇偶校验和纠错解码，从而消除了对接口中两组XOR树的需要。

2. 发明授权

US08645774B2 Expedited memory drive self test 有权
标题翻译：快速记忆体自检
公开(公告)号：US08645774B2
公开(公告)日：2014-02-04
申请号：US13323991
申请日：2011-12-13
申请人： Timothy J. Louie , Adam Roberts
发明人： Timothy J. Louie , Adam Roberts
IPC分类号： G11C29/00
CPC分类号： G11C29/04 , G11C2029/0401
摘要： Expedited memory drive self test, including: determining, by a drive self test module, a base block size for testing a memory drive; determining, by a drive self test module, a block group size for testing a memory drive; determining, by the drive self test module, a percentage of the memory drive to test; and for each block group size of memory in the memory drive: testing for media defects, by the drive self test module, a number of blocks in a block group that corresponds to the percentage of the memory drive to test.
摘要翻译：加速内存驱动器自检，包括：由驱动器自检模块确定用于测试内存驱动器的基本块大小; 由驱动器自检模块确定用于测试存储器驱动器的块组大小; 通过驱动器自检模块确定要测试的内存驱动器的百分比; 并且对于存储器驱动器中的每个块组大小的存储器：测试媒体缺陷，通过驱动器自检模块，块组中的多个块对应于要测试的存储器驱动器的百分比。

3. 发明申请

US20130151913A1 Expedited Memory Drive Self Test 有权
标题翻译：快速内存驱动器自检
公开(公告)号：US20130151913A1
公开(公告)日：2013-06-13
申请号：US13323991
申请日：2011-12-13
申请人： Timothy J. Louie , Adam Roberts
发明人： Timothy J. Louie , Adam Roberts
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/04 , G11C2029/0401
摘要： Expedited memory drive self test, including: determining, by a drive self test module, a base block size for testing a memory drive; determining, by a drive self test module, a block group size for testing a memory drive; determining, by the drive self test module, a percentage of the memory drive to test; and for each block group size of memory in the memory drive: testing for media defects, by the drive self test module, a number of blocks in a block group that corresponds to the percentage of the memory drive to test.
摘要翻译：加速内存驱动器自检，包括：由驱动器自检模块确定用于测试内存驱动器的基本块大小; 由驱动器自检模块确定用于测试存储器驱动器的块组大小; 通过驱动器自检模块确定要测试的内存驱动器的百分比; 并且对于存储器驱动器中的每个块组大小的存储器：测试媒体缺陷，通过驱动器自检模块，块组中的多个块对应于要测试的存储器驱动器的百分比。

4. 发明申请

US20120182641A1 Hard Disk Drive Availability Following Transient Vibration 失效
标题翻译：瞬态振动后的硬盘驱动器可用性
公开(公告)号：US20120182641A1
公开(公告)日：2012-07-19
申请号：US13006470
申请日：2011-01-14
申请人： Eric T. Gamble , Kenton C. Green , Carl E. Jones , Timothy J. Louie , Robert D. Peavler , David A. Verburg
发明人： Eric T. Gamble , Kenton C. Green , Carl E. Jones , Timothy J. Louie , Robert D. Peavler , David A. Verburg
IPC分类号： G11B27/36 , G11B21/02
CPC分类号： G11B5/5582 , G11B5/59694 , G11B19/042 , G11B19/209 , G11B2220/415
摘要： A method and computer program product for sending a data request from a host bus adapter logic processor to a hard disk drive, setting a standard time out period for receiving a reply from the hard disk drive, sensing vibration in the hard disk drive, sending a vibration alert signal from the hard disk drive to the host bus adapter logic processor in response to the sensed vibration exceeding a predetermined amount of vibration, and, in response to receiving the vibration alert signal from the hard disk drive, the host bus adapter logic processor establishing an extended time out period for receiving the reply. The rotational vibration sensor used by the hard disk drive for repositioning the read/write head may also be used to sense the vibration and form the basis for the vibration alert signal, such as a vibration error code. By extending the time out period during high vibration events, the hard disk drive can ride out the event without being tagged as having failed. Accordingly, the hard disk drive can then be available for use following the high vibration event.
摘要翻译：一种用于将数据请求从主机总线适配器逻辑处理器发送到硬盘驱动器的方法和计算机程序产品，设置用于从硬盘驱动器接收回复的标准超时周期，感测硬盘驱动器中的振动，发送响应于感测到的振动超过预定量的振动，从硬盘驱动器到主机总线适配器逻辑处理器的振动警报信号，并且响应于从硬盘驱动器接收到振动警报信号，主机总线适配器逻辑处理器建立收到答复的延长期限。用于重新定位读/写头的硬盘驱动器使用的旋转振动传感器也可以用于感测振动并形成诸如振动错误代码的振动警报信号的基础。通过在高振动事件期间延长超时周期，硬盘驱动器可以摆脱事件而不被标记为失败。因此，硬盘驱动器随后可以在高振动事件之后使用。

5. 发明授权

US5553306A Method and apparatus for controlling parallel port drivers in a data processing system 失效
标题翻译：用于在数据处理系统中控制并行端口驱动器的方法和装置
公开(公告)号：US5553306A
公开(公告)日：1996-09-03
申请号：US301512
申请日：1994-09-07
申请人： Margaret Claffey-Cohen , Phat T. Le , Timothy J. Louie , Alan F. Neel, II , James P. Ward
发明人： Margaret Claffey-Cohen , Phat T. Le , Timothy J. Louie , Alan F. Neel, II , James P. Ward
IPC分类号： G06F13/40 , G06F3/00 , G06F13/00
CPC分类号： G06F13/4072
摘要： A parallel port interface for utilization between a first device and a second device designated by a user for transmitting a digital signal from the device to the second device. The parallel port interface includes a switchable driver circuit for transmitting the digital signal, which includes a first circuit for emulating an open collector circuit and a second circuit for emulating a totem pole circuit. The switchable driver circuit is controlled by a logic control circuit that automatically selects either the first circuit or the second circuit for transmitting the digital signal in response to the digital signal and a designation of the second device.
摘要翻译：一种并行端口接口，用于在由用户指定的第一设备和第二设备之间利用以将数字信号从设备传输到第二设备。并行端口接口包括用于发送数字信号的可切换驱动电路，其包括用于仿真集电极开路的第一电路和用于仿真图腾柱电路的第二电路。可切换驱动器电路由逻辑控制电路控制，该逻辑控制电路响应于数字信号和第二设备的指定，自动选择第一电路或第二电路来发送数字信号。

6. 发明授权

US5239627A Bi-directional parallel printer interface 失效
标题翻译：双向平行打印机界面
公开(公告)号：US5239627A
公开(公告)日：1993-08-24
申请号：US678929
申请日：1991-03-26
申请人： James L. Beck , James R. Booth , James C. Buchanan , Margaret E. Claffey-Cohen , Carl P. Cole , Timothy J. Louie , Alan F. Neel, II , Lynn M. Oliver , James P., Ward , James F. Webb
发明人： James L. Beck , James R. Booth , James C. Buchanan , Margaret E. Claffey-Cohen , Carl P. Cole , Timothy J. Louie , Alan F. Neel, II , Lynn M. Oliver , James P., Ward , James F. Webb
IPC分类号： B41J29/38 , G06F3/12 , G06F13/42
CPC分类号： G06F3/1293 , G06F13/4226 , G06F2213/0004
摘要： A parallel interface connects a data processor and a printer so that each may transmit information to the other or receive information from the other. The transmitted information from the data processor can be data or status signals. The data or status signals are transmitted over the same eight information lines between the data processor and the printer with a predetermined signal being sent over another line from the data processor to the printer prior to transmission over the eight lines to identify whether the transmitted information is data or status signals. The printer sends status signals to the data processor over the same eight information lines after sending a predetermined signal to the data processor over a further line that it is going to transmit.

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