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1. 发明授权

US07666752B2 Deposition method for a transition-metal-containing dielectric 失效
标题翻译：含过渡金属的电介质的沉积方法
公开(公告)号：US07666752B2
公开(公告)日：2010-02-23
申请号：US11655583
申请日：2007-01-19
申请人： Stephan Kudelka , Lars Oberbeck , Uwe Schroeder , Tim Boescke , Johannes Heitmann , Annette Saenger , Joerg Schumann , Elke Erben
发明人： Stephan Kudelka , Lars Oberbeck , Uwe Schroeder , Tim Boescke , Johannes Heitmann , Annette Saenger , Joerg Schumann , Elke Erben
IPC分类号： H01L21/20
CPC分类号： H01L21/02181 , H01G4/10 , H01G4/33 , H01L21/02189 , H01L21/3141 , H01L21/31641 , H01L21/31645 , H01L27/10852 , H01L28/65
摘要： The present invention relates to a method for depositing a dielectric material comprising a transition metal compound. After providing a substrate, a first pre-cursor comprising a transition metal compound and a second pre-cursor predominantly comprising at least one of water vapour, ammonia and hydrazine are successively applied on the substrate for forming a first layer of transition metal containing material. In a next step the first pre-cursor and a third pre-cursor comprising at least one of ozone and oxygen are successively applied on the first layer for forming a second layer of the transition metal containing material.
摘要翻译：本发明涉及沉积包含过渡金属化合物的电介质材料的方法。在提供衬底之后，在衬底上依次施加包含过渡金属化合物的第一前体和主要包含水蒸汽，氨和肼中的至少一种的第二前体，形成含第一层含过渡金属的材料。在下一步骤中，在第一层上依次施加包含臭氧和氧气中的至少一种的第一前视标和第三前标，以形成含过渡金属的材料的第二层。

2. 发明申请

US20090194410A1 Electrode of an Integrated Circuit 有权
标题翻译：集成电路电极
公开(公告)号：US20090194410A1
公开(公告)日：2009-08-06
申请号：US12023321
申请日：2008-01-31
申请人： Uwe Schroeder , Stefan Jakschik , Johannes Heitmann , Tim Boescke , Annette Saender
发明人： Uwe Schroeder , Stefan Jakschik , Johannes Heitmann , Tim Boescke , Annette Saender
IPC分类号： B23H3/06
CPC分类号： H01L28/65
摘要： The present invention refers to an electrode comprising a first metallic layer and a compound comprising at least one of a nitride, oxide, and oxynitride of a second metallic material.
摘要翻译：本发明涉及包含第一金属层和包含第二金属材料的氮化物，氧化物和氧氮化物中的至少一种的化合物的电极。

3. 发明申请

US20080308896A1 Integrated circuit device comprising a gate electrode structure and corresponding method of fabrication 审中-公开
标题翻译：集成电路装置，其包括栅电极结构和相应的制造方法
公开(公告)号：US20080308896A1
公开(公告)日：2008-12-18
申请号：US11818108
申请日：2007-06-14
申请人： Tim Boescke
发明人： Tim Boescke
IPC分类号： H01L21/4763 , H01L29/00
CPC分类号： H01L21/823842 , H01L21/28194 , H01L27/092 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： The present invention provides an integrated circuit device comprising a semiconductor substrate and a gate electrode structure on the semiconductor substrate having at least one insulating layer of dielectric material on said semiconductor substrate and a metal layer on said at least one insulating layer, said metal layer containing niobium (Nb), vanadium (V), chromium (Cr), tungsten (W) and/or molybdenum (Mo).
摘要翻译：本发明提供了一种集成电路器件，其包括在半导体衬底上的半导体衬底和栅电极结构，在所述半导体衬底上具有至少一个介电材料绝缘层，并且在所述至少一个绝缘层上具有金属层，所述金属层含有铌（Nb），钒（V），铬（Cr），钨（W）和/或钼（Mo）。

4. 发明授权

US08344438B2 Electrode of an integrated circuit 有权
标题翻译：集成电路的电极
公开(公告)号：US08344438B2
公开(公告)日：2013-01-01
申请号：US12023321
申请日：2008-01-31
申请人： Uwe Schroeder , Stefan Jakschik , Johannes Heitmann , Tim Boescke , Annette Saenger
发明人： Uwe Schroeder , Stefan Jakschik , Johannes Heitmann , Tim Boescke , Annette Saenger
IPC分类号： H01L27/108 , H01L29/94 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L28/65
摘要： The present invention refers to an electrode comprising a first metallic layer and a compound comprising at least one of a nitride, oxide, and oxynitride of a second metallic material.
摘要翻译：本发明涉及包含第一金属层和包含第二金属材料的氮化物，氧化物和氧氮化物中的至少一种的化合物的电极。

5. 发明授权

US08304823B2 Integrated circuit including a ferroelectric memory cell and method of manufacturing the same 有权
标题翻译：包括铁电存储单元的集成电路及其制造方法
公开(公告)号：US08304823B2
公开(公告)日：2012-11-06
申请号：US12106741
申请日：2008-04-21
申请人： Tim Boescke
发明人： Tim Boescke
IPC分类号： H01L21/02
CPC分类号： H01L21/28291 , G11C11/22 , G11C11/223 , H01L21/31641 , H01L21/31645 , H01L28/55 , H01L29/0673 , H01L29/516 , H01L29/78391 , H01L29/785
摘要： A method for manufacturing an integrated circuit including a ferroelectric memory cell is disclosed. One embodiment of the method includes: forming a amorphous oxide layer over a carrier, the amorphous layer including: O and any of the group of: Hf, Zr and (Hf,Zr), forming a covering layer on the amorphous layer, and heating the amorphous layer up to a temperature above its crystallization temperature to at least partly alter its crystal state from amorphous to crystalline, resulting in a crystallized oxide layer.
摘要翻译：公开了一种制造包括铁电存储器单元的集成电路的方法。该方法的一个实施例包括：在载体上形成无定形氧化物层，所述非晶层包括：O和Hf，Zr和（Hf，Zr）中的任何一种，在非晶层上形成覆盖层，以及加热该非晶层达到高于其结晶温度的温度，以至少部分地将其晶体状态从无定形改变为结晶状态，导致结晶的氧化物层。

6. 发明授权

US07723771B2 Zirconium oxide based capacitor and process to manufacture the same 有权
标题翻译：基于氧化锆的电容器及其制造方法
公开(公告)号：US07723771B2
公开(公告)日：2010-05-25
申请号：US11731457
申请日：2007-03-30
申请人： Tim Boescke , Uwe Schroeder
发明人： Tim Boescke , Uwe Schroeder
IPC分类号： H01L27/108
CPC分类号： H01G4/1236 , H01G4/33 , H01L28/40 , Y10T29/417
摘要： A capacitor structure comprises a first and a second electrode of conducting material. Between the first and second electrodes, an atomic layer deposited dielectric film is disposed, which comprises zirconium oxide and a dopant oxide. Herein, the dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, while the dielectric film comprises a dopant content of 10 atomic percent or less of the dielectric film material excluding oxygen. A process for fabricating a capacitor comprises a step of forming a bottom electrode of the capacitor. On the bottom electrode, a dielectric film comprising zirconium oxide is deposited, and a step for introducing a dopant oxide into the dielectric film performed. On the dielectric structure, a top electrode is formed. The dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, whereas the dielectric structure deposited comprises a dopant content of 10 atomic percent or less of the deposited material excluding oxygen.
摘要翻译：电容器结构包括导电材料的第一和第二电极。在第一和第二电极之间，设置原子层沉积介电膜，其包括氧化锆和掺杂剂氧化物。这里，掺杂剂包含从锆的离子半径相差大于24μm的离子半径，而电介质膜包含不含氧的电介质膜材料的10原子％以下的掺杂剂含量。制造电容器的工艺包括形成电容器的底部电极的步骤。在底部电极上沉积包含氧化锆的电介质膜，并且进行用于将掺杂剂氧化物引入电介质膜的步骤。在电介质结构上，形成顶部电极。掺杂剂包含距离锆的离子半径相差超过24μm的离子半径，而沉积的介电结构包括不含氧的沉积材料的10原子％以下的掺杂剂含量。

7. 发明申请

US20100006953A1 INTEGRATED CIRCUIT INCLUDING A DIELECTRIC LAYER 有权
标题翻译：集成电路，包括电介质层
公开(公告)号：US20100006953A1
公开(公告)日：2010-01-14
申请号：US12170967
申请日：2008-07-10
申请人： Tim Boescke
发明人： Tim Boescke
IPC分类号： H01L29/423 , H01L21/28 , H01L29/78
CPC分类号： H01L28/55 , G11C11/22 , H01L27/10876 , H01L28/40 , H01L28/75 , H01L28/91 , H01L29/517
摘要： An integrated circuit including a dielectric layer and a method for manufacturing. One embodiment provides a substrate having a first side and a second side and at least one dielectric layer. The dielectric layer includes a zirconium oxide and at least one dopant selected from the group consisting of hafnium and titanium and having a first side and a second side. The first side of the dielectric layer is arranged at least on a subarea of the first side of the semiconductor substrate.
摘要翻译：包括电介质层的集成电路和制造方法。一个实施例提供了具有第一侧和第二侧以及至少一个电介质层的衬底。电介质层包括氧化锆和选自铪和钛的至少一种掺杂剂并具有第一面和第二面。电介质层的第一侧至少布置在半导体衬底的第一侧的子区域上。

8. 发明授权

US07709359B2 Integrated circuit with dielectric layer 有权
标题翻译：集成电路与介质层
公开(公告)号：US07709359B2
公开(公告)日：2010-05-04
申请号：US11850218
申请日：2007-09-05
申请人： Tim Boescke , Johannes Heitmann , Uwe Schroder
发明人： Tim Boescke , Johannes Heitmann , Uwe Schroder
IPC分类号： H01L29/72
CPC分类号： H01L21/28291 , H01L27/10873 , H01L28/40 , H01L28/91 , H01L29/513 , H01L29/78
摘要： A method of fabricating an integrated circuit with a dielectric layer on a substrate is disclosed. One embodiment provides forming the dielectric layer in an amorphous state on the substrate, the dielectric layer having a crystallization temperature; a doping the dielectric layer; a forming of a covering layer on the dielectric layer at a temperature being equal to or below the crystallization temperature; and a heating of the dielectric layer to a temperature being equal to or greater than the crystallization temperature.
摘要翻译：公开了一种在衬底上制造具有电介质层的集成电路的方法。一个实施例提供在基底上形成非晶状态的电介质层，介电层具有结晶温度; 掺杂介电层; 在等于或低于结晶温度的温度下在电介质层上形成覆盖层; 以及将介电层加热至等于或大于结晶温度的温度。

9. 发明申请

US20090057737A1 INTEGRATED CIRCUIT WITH DIELECTRIC LAYER 有权
标题翻译：集成电路与电介质层
公开(公告)号：US20090057737A1
公开(公告)日：2009-03-05
申请号：US11850218
申请日：2007-09-05
申请人： Tim Boescke , Johannes Heitmann , Uwe Schroder
发明人： Tim Boescke , Johannes Heitmann , Uwe Schroder
IPC分类号： H01L29/76 , H01L21/00
CPC分类号： H01L21/28291 , H01L27/10873 , H01L28/40 , H01L28/91 , H01L29/513 , H01L29/78
摘要： A method of fabricating an integrated circuit with a dielectric layer on a substrate is disclosed. One embodiment provides forming the dielectric layer in an amorphous state on the substrate, the dielectric layer having a crystallization temperature; a doping the dielectric layer; a forming of a covering layer on the dielectric layer at a temperature being equal to or below the crystallization temperature; and a heating of the dielectric layer to a temperature being equal to or greater than the crystallization temperature.
摘要翻译：公开了一种在衬底上制造具有电介质层的集成电路的方法。一个实施例提供在基底上形成非晶状态的电介质层，介电层具有结晶温度; 掺杂介电层; 在等于或低于结晶温度的温度下在电介质层上形成覆盖层; 以及将介电层加热至等于或大于结晶温度的温度。

10. 发明申请

US20080242097A1 Selective deposition method 审中-公开
标题翻译：选择性沉积法
公开(公告)号：US20080242097A1
公开(公告)日：2008-10-02
申请号：US11729360
申请日：2007-03-28
申请人： Tim Boescke , Annette Saenger , Stefan Jakschik , Christian Fachmann , Matthias Patz , Alejandro Avellan , Thomas Hecht , Jonas Sundqvist
发明人： Tim Boescke , Annette Saenger , Stefan Jakschik , Christian Fachmann , Matthias Patz , Alejandro Avellan , Thomas Hecht , Jonas Sundqvist
IPC分类号： H01L21/31 , H01L29/06
CPC分类号： H01L29/945 , C30B25/04 , H01L21/02148 , H01L21/02159 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/0228 , H01L21/02304 , H01L21/31604 , H01L21/31612 , H01L21/31616 , H01L21/31645
摘要： The invention refers to a selective deposition method. A substrate comprising at least one structured surface is provided. The structured surface comprises a first area and a second area. The first area is selectively passivated regarding reactants of a first deposition technique and the second area is activated regarding the reactants the first deposition technique. A passivation layer on the second area is deposited via the first deposition technique. The passivation layer is inert regarding a precursors selected from a group of oxidizing reactants. A layer is deposited in the second area using a second atomic layer deposition technique as second deposition technique using the precursors selected form the group of oxidizing reactants.
摘要翻译：本发明涉及选择性沉积方法。提供了包括至少一个结构化表面的衬底。结构化表面包括第一区域和第二区域。对于第一沉积技术的反应物，第一区域被选择性地钝化，并且第二区域被激活关于第一沉积技术的反应物。通过第一沉积技术沉积第二区域上的钝化层。对于选自一组氧化反应物的前体，钝化层是惰性的。使用第二原子层沉积技术将层沉积在第二区域中，作为使用从氧化反应物组中选择的前体的第二沉积技术。

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