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1. 发明授权

US08255607B2 SAS expander-based SAS/SATA bridging 有权
标题翻译：基于SAS扩展器的SAS / SATA桥接
公开(公告)号：US08255607B2
公开(公告)日：2012-08-28
申请号：US12613390
申请日：2009-11-05
申请人： Marc Timothy Jones , Murthy Kompella , Thomas Vincent Spencer , Carl Joseph Mies , Sammy Dwayne Sawyer
发明人： Marc Timothy Jones , Murthy Kompella , Thomas Vincent Spencer , Carl Joseph Mies , Sammy Dwayne Sawyer
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F13/4027 , G06F2213/0028 , G06F2213/0032
摘要： Described herein is an improved mechanism for bridging between SAS and SATA drives based upon existing SAS expanders in a SAS domain. In particular, a bridge capable of translating between SAS and SATA protocols is embedded in or coupled to an expander. When a SAS initiator request is received at the expander, the expander can route the request, based on a routing table, either directly to a destination SAS device or to the bridge for necessary translation before it is transmitted to a destination SATA drive. The routing table includes corresponding relationships between all SAS addresses and Phys through which those SAS and SATA devices are attached to the expander. SATA devices can be virtualized in the expander through a few assigned addresses in the routing table in a SAS discovery process.
摘要翻译：这里描述了一种基于SAS域中的现有SAS扩展器来桥接SAS和SATA驱动器的改进机制。特别地，能够在SAS和SATA协议之间转换的桥嵌入或耦合到扩展器。当在扩展器处接收到SAS发起者请求时，扩展器可以在将路由表发送到目的地SATA驱动器之前，将路由表直接路由到目标SAS设备或桥接器进行必要的转换。路由表包括所有SAS地址和Phys之间的对应关系，通过它们将这些SAS和SATA设备连接到扩展器。 SATA设备可以在SAS发现过程中通过路由表中的几个分配的地址在扩展器中进行虚拟化。

2. 发明授权

US07058735B2 Method and apparatus for local and distributed data memory access (“DMA”) control 有权
标题翻译：本地和分布式数据存储器访问（“DMA”）控制的方法和装置
公开(公告)号：US07058735B2
公开(公告)日：2006-06-06
申请号：US10452330
申请日：2003-06-02
申请人： Thomas Vincent Spencer
发明人： Thomas Vincent Spencer
IPC分类号： G06F13/00
CPC分类号： G06F13/28
摘要： An apparatus for local direct memory access control includes a processor unit for generating a direct memory access designator when needed data is not available and continuing processing which does not require the unavailable data. A memory access designator holder receives the memory access designator, and a local data memory access controller performs a data memory access transaction in accordance with the content of a descriptor. Staging registers hold components of a data memory access designator and transfer the components to a selected portion of the data memory access designator holder. The data memory access controller transfers the contents of the staging registers to the data memory access designator holder when one of the staging registers is written to by the processor unit. The processor unit stalls if a write to the staging register occurs when the data memory access designator holders contain a data memory access designator, and ceases the stall when one of the plurality of data memory access designator holders ceases to contain a data memory access designator.
摘要翻译：用于本地直接存储器访问控制的装置包括处理器单元，用于当需要数据不可用时生成直接存储器访问指示符，并且不需要不可用数据的持续处理。存储器访问指示符持有者接收存储器访问指示符，并且本地数据存储器访问控制器根据描述符的内容执行数据存储器访问事务。分段寄存器保存数据存储器访问指示符的组件，并将组件传输到数据存储器访问指示符持有者的选定部分。数据存储器访问控制器在处理器单元写入其中一个分段寄存器时，将分段寄存器的内容传送到数据存储器访问指示符持有者。如果在数据存储器访问指示符持有者包含数据存储器访问指示符时发生对分段寄存器的写入，则处理器单元停止，并且当多个数据存储器访问指示符持有者之一停止包含数据存储器访问指示符时，停止停止。

3. 发明授权

US06912610B2 Hardware assisted firmware task scheduling and management 有权
标题翻译：硬件辅助固件任务调度和管理
公开(公告)号：US06912610B2
公开(公告)日：2005-06-28
申请号：US10402182
申请日：2003-03-28
申请人： Thomas Vincent Spencer
发明人： Thomas Vincent Spencer
IPC分类号： G06F20060101 , G06F9/00 , G06F9/46 , G06F9/50 , G06F13/38
CPC分类号： G06F9/546 , G06F2209/548
摘要： A data processing module having a central processing unit and a task management control method and apparatus is disclosed which may comprise: a plurality of task identifiers adapted to identify a task requesting service by the central processing unit; an arbitration system external to the central processing unit adapted to select a task identifier from one of the plurality of task identifiers and to provide to the central processing unit the location of data or at least one instruction, which location is determined by the identity of the task identifier and to provide to the central processing unit the location of at least one instruction to initiate processing of the task, comprising: arbitration value determination logic adapted to determine at least one arbitration value of each task identifier requesting service; arbitration logic adapted to select a task identifier requesting service based upon the at least one arbitration value for each task identifier requesting service.
摘要翻译：公开了一种具有中央处理单元和任务管理控制方法和装置的数据处理模块，其可以包括：多个任务标识符，用于识别中央处理单元的任务请求服务; 中央处理单元外部的仲裁系统，适于从多个任务标识符之一选择任务标识符，并向中央处理单元提供数据或至少一个指令的位置，哪个位置由任务标识符，并且向中央处理单元提供至少一个指令以发起任务处理的位置，包括：仲裁值确定逻辑，适于确定每个任务标识符请求服务的至少一个仲裁值; 仲裁逻辑适于基于每个任务标识符请求服务的至少一个仲裁值来选择任务标识符请求服务。

4. 发明授权

US06880047B2 Local emulation of data RAM utilizing write-through cache hardware within a CPU module 有权
标题翻译：使用CPU模块内的直写缓存硬件对数据RAM进行本地仿真
公开(公告)号：US06880047B2
公开(公告)日：2005-04-12
申请号：US10401459
申请日：2003-03-28
申请人： Thomas Vincent Spencer
发明人： Thomas Vincent Spencer
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0802 , G06F12/0888 , G06F12/126 , G06F2212/2515
摘要： In a processor module having a local software visible data memory and a write through cache connected to an external memory space external to the processor module over a bus, a method and apparatus for supplementing the local software visible data memory utilizing the write through cache is disclosed which may comprise: a processor bus interface and memory management unit adapted to detect a processor write operation to a preselected location in the external memory space that is not currently a cached address line, that will cause a cache miss, to decode the write operation to the preselected external memory space location as a RAM emulation write operation and to place in the cache pseudo data at the respective address line in the cache, without executing a fetch and store from the actual external memory location in response to the cache miss. The method and apparatus may further comprise the processor bus interface and memory management unit further adapted to subsequently ignore the write through command from the processor when the processor writes to the address without a cache miss. The external memory space may include a cacheable portion of external memory space and a non-cacheable portion of the external memory space; and, the preselected external memory space may be located within the cacheable portion of the external memory space. The module may be implemented on an integrated circuit and comprise a portion of a computer and communication link interface and may include a plurality of modules and may be contained on a host bus adapter card.
摘要翻译：在具有本地软件可视数据存储器和通过总线连接到处理器模块外部的外部存储器空间的写入高速缓存的处理器模块中，公开了一种利用写入高速缓存来补充本地软件可视数据存储器的方法和装置其可以包括：处理器总线接口和存储器管理单元，其适于检测对外部存储器空间中的当前未被缓存的地址线的预选位置的处理器写入操作，这将导致高速缓存未命中，以将写操作解码为预选的外部存储器空间位置作为RAM仿真写入操作，并且在高速缓存中的相应地址线处放置在高速缓存伪数据中，而不响应于高速缓存未命中而从实际外部存储器位置执行获取和存储。该方法和装置还可以包括处理器总线接口和存储器管理单元，该处理器总线接口和存储器管理单元进一步适于随后当处理器写入地址而忽略高速缓存时随后忽略来自处理器的写入命令。外部存储器空间可以包括外部存储器空间的可高速缓存部分和外部存储器空间的不可高速缓存部分; 并且预选的外部存储器空间可以位于外部存储器空间的可高速缓存部分内。模块可以在集成电路上实现并且包括计算机的一部分和通信链路接口，并且可以包括多个模块并且可以包含在主机总线适配器卡上。

5. 发明申请

US20110107002A1 SAS Expander-Based SAS/SATA Bridging 有权
标题翻译：基于SAS扩展器的SAS / SATA桥接
公开(公告)号：US20110107002A1
公开(公告)日：2011-05-05
申请号：US12613390
申请日：2009-11-05
申请人： Marc Timothy JONES , Murthy Kompella , Thomas Vincent Spencer , Carl Joseph Mies , Sammy Dwayne Sawyer
发明人： Marc Timothy JONES , Murthy Kompella , Thomas Vincent Spencer , Carl Joseph Mies , Sammy Dwayne Sawyer
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F2213/0028 , G06F2213/0032
摘要： Described herein is an improved mechanism for bridging between SAS and SATA drives based upon existing SAS expanders in a SAS domain. In particular, a bridge capable of translating between SAS and SATA protocols is embedded in or coupled to an expander. When a SAS initiator request is received at the expander, the expander can route the request, based on a routing table, either directly to a destination SAS device or to the bridge for necessary translation before it is transmitted to a destination SATA drive. The routing table includes corresponding relationships between all SAS addresses and Phys through which those SAS and SATA devices are attached to the expander. SATA devices can be virtualized in the expander through a few assigned addresses in the routing table in a SAS discovery process.
摘要翻译：这里描述了一种基于SAS域中的现有SAS扩展器来桥接SAS和SATA驱动器的改进机制。特别地，能够在SAS和SATA协议之间转换的桥嵌入或耦合到扩展器。当在扩展器处接收到SAS发起者请求时，扩展器可以在将路由表发送到目的地SATA驱动器之前，将路由表直接路由到目标SAS设备或桥接器进行必要的转换。路由表包括所有SAS地址和Phys之间的对应关系，通过它们将这些SAS和SATA设备连接到扩展器。 SATA设备可以在SAS发现过程中通过路由表中的几个分配的地址在扩展器中进行虚拟化。

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