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1. 发明授权

US08218518B2 Interleaver interface for a software-defined radio system 失效
标题翻译：用于软件定义无线电系统的交织器接口
公开(公告)号：US08218518B2
公开(公告)日：2012-07-10
申请号：US11750742
申请日：2007-05-18
申请人： Eran Pisek , Thomas M. Henige
发明人： Eran Pisek , Thomas M. Henige
IPC分类号： H04B7/216
CPC分类号： H04L1/0055 , H03M13/27 , H03M13/2957 , H03M13/3905 , H03M13/6519 , H04L1/0071
摘要： A software-defined radio (SDR) system that operates under a plurality of wireless communication standards. The SDR system comprises a reconfigurable maximum aposteriori probability (MAP) decoder capable of being configured under software control to decode a received data block according to a select wireless communication standard and a reconfigurable interleaver associated with the reconfigurable MAP decoder. The reconfigurable interleaver comprises a reconfigurable interleaver core circuitry capable of being configured under software control to operate according to the selected wireless communication standard and a unified interleaver interface for coupling a defined set of control and bus signals from the reconfigurable MAP decoder to the reconfigurable interleaver core circuitry.
摘要翻译：一种在多种无线通信标准下工作的软件定义无线电（SDR）系统。 SDR系统包括可配置在软件控制下的可重配置最大后验概率（MAP）解码器，以根据选择无线通信标准对接收到的数据块进行解码，以及与可重新配置的MAP解码器相关联的可重配置交织器。可重配置交织器包括能够被配置在软件控制下以根据所选择的无线通信标准进行操作的可重配置交织器核心电路和统一的交织器接口，用于将定义的一组控制和总线信号从可重新配置的MAP解码器耦合到可重配置交织器核心电路。

2. 发明授权

US09634693B2 Apparatus and method for decoding LDPC codes in a communications system 有权
公开(公告)号：US09634693B2
公开(公告)日：2017-04-25
申请号：US13248900
申请日：2011-09-29
申请人： Eran Pisek , Shadi Abu-Surra , Thomas M. Henige
发明人： Eran Pisek , Shadi Abu-Surra , Thomas M. Henige
IPC分类号： H03M13/00 , H03M13/31 , H03M13/03 , H03M13/11
CPC分类号： H03M13/31 , H03M13/033 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/118
摘要： An apparatus and method decode LDPC code. The apparatus includes a memory and a number of LDPC processing elements. The memory is configured to receive a LDPC codeword having a length equal to a lifting factor times a base LDPC code length, wherein the lifting factor is greater than one. The number of LDPC processing elements configured to decode the LDPC codeword, wherein each of the number of LDPC processing elements decode separate portions of the LDPC codeword.

3. 发明授权

US08627166B2 LDPC code family for millimeter-wave band communications in a wireless network 有权
标题翻译：用于无线网络中毫米波段通信的LDPC码系列
公开(公告)号：US08627166B2
公开(公告)日：2014-01-07
申请号：US13306747
申请日：2011-11-29
申请人： Shadi Abu-Surra , Thomas M. Henige , Eran Pisek , Zhouyue Pi
发明人： Shadi Abu-Surra , Thomas M. Henige , Eran Pisek , Zhouyue Pi
IPC分类号： H03M13/00
CPC分类号： H03M13/618 , H03M13/033 , H03M13/036 , H03M13/1137 , H03M13/116 , H03M13/6516
摘要： A method constructs a family of low-density-parity-check (LDPC) codes. The method includes identifying a code rate for an LDPC code in the family, identifying a protograph for the LDPC code, and constructing a base matrix for the LDPC code. The base matrix is constructed by replacing each zero in the protograph with a ‘−1’, selecting a corresponding value for an absolute shift for each one in the protograph based on constraining a number of relative shifts per column of the LDPC code to one and increasing a size of a smallest cycle in a graph of the LDPC code, and replacing each one in the protograph with the corresponding value.
摘要翻译：一种方法构建了一系列低密度奇偶校验（LDPC）码。该方法包括识别该系列中的LDPC码的码率，识别LDPC码的原型图，以及构造LDPC码的基本矩阵。基本矩阵是通过用“-1”代替原型图中的每个零来构造的，基于将每个LDPC码的相对位移数量约束为1，为了对原型图中的每一个选择相应的绝对位移值，增加LDPC码的图形中的最小周期的大小，并将原型图中的每一个替换为相应的值。

4. 发明授权

US08606259B2 Method and system for testing a software-defined radio device 失效
标题翻译：用于测试软件定义无线电设备的方法和系统
公开(公告)号：US08606259B2
公开(公告)日：2013-12-10
申请号：US11655471
申请日：2007-01-19
申请人： Thirumalarao Voonna , Jasmin Oz , Eran Pisek , Thomas M. Henige
发明人： Thirumalarao Voonna , Jasmin Oz , Eran Pisek , Thomas M. Henige
IPC分类号： H04W24/00
CPC分类号： H04B17/0085
摘要： A method for testing a software-defined radio (SDR) device is provided. The method includes configuring the SDR device for a first standard. A first test is performed on the SDR device under the first standard. Test data for the first test is received from the SDR device. A switching time for configuring the SDR device for the first standard is determined based on the test data for the first test.
摘要翻译：提供了一种用于测试软件定义无线电（SDR）设备的方法。该方法包括为第一标准配置SDR设备。在第一个标准的SDR设备上执行第一个测试。从SDR设备接收第一次测试的测试数据。基于第一测试的测试数据来确定用于配置用于第一标准的SDR设备的切换时间。

5. 发明申请

US20120240001A1 LDPC CODE FAMILY FOR MILLIMETER-WAVE BAND COMMUNICATIONS IN A WIRELESS NETWORK 有权
标题翻译：用于无线网络中的毫米波段通信的LDPC码系列
公开(公告)号：US20120240001A1
公开(公告)日：2012-09-20
申请号：US13306747
申请日：2011-11-29
申请人： Shadi Abu-Surra , Thomas M. Henige , Eran Pisek , Zhouyue Pi
发明人： Shadi Abu-Surra , Thomas M. Henige , Eran Pisek , Zhouyue Pi
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/618 , H03M13/033 , H03M13/036 , H03M13/1137 , H03M13/116 , H03M13/6516
摘要： A method constructs a family of low-density-parity-check (LDPC) codes. The method includes identifying a code rate for an LDPC code in the family, identifying a protograph for the LDPC code, and constructing a base matrix for the LDPC code. The base matrix is constructed by replacing each zero in the protograph with a ‘−1’, selecting a corresponding value for an absolute shift for each one in the protograph based on constraining a number of relative shifts per column of the LDPC code to one and increasing a size of a smallest cycle in a graph of the LDPC code, and replacing each one in the protograph with the corresponding value.
摘要翻译：一种方法构建了一系列低密度奇偶校验（LDPC）码。该方法包括识别该系列中的LDPC码的码率，识别LDPC码的原型图，以及构造LDPC码的基本矩阵。基本矩阵是通过用“-1”代替原型图中的每个零来构造的，基于将每个LDPC码的相对位移数量约束为1，为了对原型图中的每一个选择相应的绝对位移值，增加LDPC码的图形中的最小周期的大小，并将原型图中的每一个替换为相应的值。

6. 发明申请

US20120084625A1 APPARATUS AND METHOD FOR DECODING LDPC CODES IN A COMMUNICATIONS SYSTEM 有权
标题翻译：用于解码通信系统中的LDPC码的装置和方法
公开(公告)号：US20120084625A1
公开(公告)日：2012-04-05
申请号：US13248900
申请日：2011-09-29
申请人： Eran Pisek , Shadi Abu-Surra , Thomas M. Henige
发明人： Eran Pisek , Shadi Abu-Surra , Thomas M. Henige
IPC分类号： H03M13/00 , G06F11/08
CPC分类号： H03M13/31 , H03M13/033 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/118
摘要： An apparatus and method decode LDPC code. The apparatus includes a memory and a number of LDPC processing elements. The memory is configured to receive a LDPC codeword having a length equal to a lifting factor times a base LDPC code length, wherein the lifting factor is greater than one. The number of LDPC processing elements configured to decode the LDPC codeword, wherein each of the number of LDPC processing elements decode separate portions of the LDPC codeword.
摘要翻译：一种解码LDPC码的装置和方法。该装置包括存储器和多个LDPC处理元件。存储器被配置为接收长度等于提升因子乘以基本LDPC码长度的LDPC码字，其中提升因子大于1。被配置为对LDPC码字进行解码的LDPC处理单元的数量，其中，所述多个LDPC处理单元中的每一个解码所述LDPC码字的分离部分。

7. 发明授权

US08032811B2 Efficient almost regular permutation (ARP) interleaver and method 有权
标题翻译：高效的几乎规则排列（ARP）交织器和方法
公开(公告)号：US08032811B2
公开(公告)日：2011-10-04
申请号：US11715202
申请日：2007-03-07
申请人： Thomas M. Henige , Eran Pisek
发明人： Thomas M. Henige , Eran Pisek
IPC分类号： H03M13/03
CPC分类号： H03M13/2764 , H03M13/2753 , H03M13/2957 , H03M13/6508
摘要： An almost regular permutation (ARP) interleaver and method generate interleaved indices in a sequential fashion based on a process in which each interleaved index is a function of an adjacent index. Based on the data block size (N) for a received data block and a constant (C) for the ARP interleaver, a plurality of interleaved indices is generated. For one embodiment in which the interleaved indices are generated in forward sequence, the adjacent interleaved index is the immediately previous index, P(j−1), and each interleaved index (P(j)) is generated based on incrementing the previous interleaved index (P(j−1)) by an incremental value k(i), where j represents a non-interleaved index between 0 and N−1, i represents a modulo-C counter index that corresponds to j, k(i) represents the i-th value of a set of incremental values associated with N and C.
摘要翻译：几乎常规排列（ARP）交织器和方法基于其中每个交织索引是相邻索引的函数的过程以顺序方式产生交错索引。基于接收数据块的数据块大小（N）和用于ARP交织器的常数（C），生成多个交织索引。对于其中以正向序列生成交织索引的一个实施例，相邻交织索引是紧接在前的索引P（j-1），并且每个交织索引（P（j））是基于递增先前的交织索引（P（j-1））乘以增量值k（i），其中j表示0和N-1之间的非交织索引，i表示对应于j的模C计数器索引，k（i）表示与N和C相关联的一组增量值的第i个值。

8. 发明申请

US20090144353A1 Method and apparatus for efficient modulo multiplication 失效
标题翻译：用于有效模乘的方法和装置
公开(公告)号：US20090144353A1
公开(公告)日：2009-06-04
申请号：US12216896
申请日：2008-07-11
申请人： Eran Pisek , Thomas M. Henige
发明人： Eran Pisek , Thomas M. Henige
IPC分类号： G06F7/38
CPC分类号： G06F7/728
摘要： A method of a hardware based Montgomery reduction contemplates preparing a table comprising a plurality of sets of values of 2K+i (mod n), 2K+i+1 (mod n) and (2K+i+2K+i+1)(mod n), where i=to M−2, n is a modulo number, K is an integer, and M is a number of significant bits in a binary Y; selecting one of the values within one of the plurality of sets of the table in dependence upon a value of two neighboring bits Yi+1,i of the binary Y; adding two neighboring selected values and calculating the modulo value of the sum value with the modulo number n; repeatedly adding two neighboring calculated modulo values and calculating the modulo value of the intermediate sum of the two neighboring calculated modulo values until only a single calculated module value is obtained; and setting the single value as the Montgomery representation.
摘要翻译：一种基于硬件的Montgomery减少方法考虑准备包括多个值的组2K + i（mod n），2K + i + 1（mod n）和（2K + i + 2K + i + 1）（ mod n），其中i =到M-2，n是模数，K是整数，M是二进制Y中的有效位数; 根据二进制Y的两个相邻位Yi + 1，i的值，选择该表的多个集合之一内的值之一; 加上两个相邻的选择值，并用模数n计算求和值的模数; 反复添加两个相邻的计算的模数值，并计算两个相邻计算的模数值的中间和的模数，直到仅获得单个计算的模块值; 并将单个值设置为蒙哥马利表示。

9. 发明申请

US20080123781A1 Apparatus and method using reduced memory for channel decoding in a software-defined radio system 有权
标题翻译：在软件定义的无线电系统中使用减少的存储器用于信道解码的装置和方法
公开(公告)号：US20080123781A1
公开(公告)日：2008-05-29
申请号：US11605525
申请日：2006-11-29
申请人： Eran Pisek , Thomas M. Henige
发明人： Eran Pisek , Thomas M. Henige
IPC分类号： H04L27/06 , G06F11/07
CPC分类号： H04L1/0055 , H03M13/2969 , H03M13/3905 , H03M13/3911 , H03M13/3972 , H03M13/3983 , H03M13/6569 , H04L1/005 , H04L1/0052 , H04L1/0057 , H04L1/0066
摘要： A maximum a posteriori probability (MAP) block decoder for decoding a received data block of input samples. The MAP block decoder segments the received data block into at least a first segment and a second segment and calculates and stores alpha values during forward processing of the first segment. The MAP block decoder uses a first selected alpha value calculated during forward processing of the first segment as initial state information during forward processing of the second segment. The first and second segments may overlap each other, such that the last M samples of the first segment are the same as the first M samples of the second segment.
摘要翻译：用于对输入样本的接收数据块进行解码的最大后验概率（MAP）块解码器。 MAP块解码器将接收的数据块分段成至少第一段和第二段，并且在第一段的正向处理期间计算并存储α值。 MAP块解码器使用在第一段的正向处理期间计算的第一选择的α值作为第二段的正向处理期间的初始状态信息。第一和第二段可以彼此重叠，使得第一段的最后M个样本与第二段的前M个样本相同。

10. 发明申请

US20080115032A1 Efficient almost regular permutation (ARP) interleaver and method 有权
标题翻译：高效的几乎规则排列（ARP）交织器和方法
公开(公告)号：US20080115032A1
公开(公告)日：2008-05-15
申请号：US11715202
申请日：2007-03-07
申请人： Thomas M. Henige , Eran Pisek
发明人： Thomas M. Henige , Eran Pisek
IPC分类号： H03M13/00
CPC分类号： H03M13/2764 , H03M13/2753 , H03M13/2957 , H03M13/6508
摘要： A method for operating an ARP interleaver is provided that includes generating each of a plurality of interleaved indices, P(j), as a function of an adjacent interleaved index. For one embodiment, the adjacent interleaved index is the immediately previous index, P(j−1), and each of the interleaved indices, P(j), is generated based on the following formula: P(j)=[P(j−1)+P0+d(j)−d(j−1)]mod N, where N comprises a data block size, P0 comprises a constant that is dependent on N, and d(j) comprises a dither vector.
摘要翻译：提供了一种用于操作ARP交织器的方法，其包括生成作为相邻交织索引的函数的多个交织索引P（j）中的每一个。对于一个实施例，相邻交错索引是紧接在前的索引P（j-1），并且基于以下公式生成交织索引P（j）中的每一个：P（j）= [P（j -1）+ P <0> d（j）-d（j-1）] mod N，其中N包括数据块大小，P <0>包括常数，取决于N，并且d（j）包括抖动矢量。

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