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    • 1. 发明授权
    • Data processor system clock checking system
    • 数据处理器系统时钟检查系统
    • US4482819A
    • 1984-11-13
    • US342270
    • 1982-01-25
    • Bharat J. OzaThomas J. Roche
    • Bharat J. OzaThomas J. Roche
    • G06F1/10H03L7/00H03L1/00
    • G06F1/10
    • A central clock signal generator generates a plurality of odd and even clock pulses which are distributed to a plurality of logic and circuit modules by clock signal lines of equal length. The central signal generator also generates a plurality of gate pulses which are supplied to the modules on signal lines which can be different in length from one to another. The gate pulses are wide enough to coincide with the clock pulses with appropriate allowance for skew between the pulses. For each pair of pulses engaged delivered to a module a detection circuit is provided which detects if the gate pulse and the clock pulse begin and end in the proper sequence. If an improper sequence occurs, the information is stored in a scannable latch and a machine stop control is generated. The exact failing module can be traced readily from the information supplied in this manner.
    • 中央时钟信号发生器产生多个奇数和偶数时钟脉冲,这些脉冲通过相等长度的时钟信号线分配给多个逻辑电路和电路模块。 中央信号发生器还产生多个门脉冲,其被提供给信号线上的模块,该信号线可以在长度上彼此不同。 门脉冲宽度足以与时钟脉冲重合,适当地允许脉冲之间的偏移。 对于被馈送到模块的每对脉冲对,提供检测电路,其检测门脉冲和时钟脉冲是否以适当的顺序开始和结束。 如果发生不正确的顺序,信息存储在可扫描的锁存器中,并产生机器停止控制。 可以从以这种方式提供的信息中容易地跟踪确切的故障模块。