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1. 发明申请

US20080244366A1 ADAPTABLE CHANNEL COMPENSATION FOR RELIABLE COMMUNICATION OVER FADING COMMUNICATION LINKS 有权
标题翻译：适应性通道补偿通过通信链接进行可靠通信
公开(公告)号：US20080244366A1
公开(公告)日：2008-10-02
申请号：US12115720
申请日：2008-05-06
申请人： Thomas H. Friddell
发明人： Thomas H. Friddell
IPC分类号： G06F11/07
CPC分类号： H03M13/2789 , H03M13/15 , H03M13/1515 , H03M13/2732 , H03M13/2936 , H03M13/2957 , H03M13/353 , H03M13/6508 , H03M13/6561 , H03M13/6566
摘要： A method for reducing fading channel signal data loss for serial data rates rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.
摘要翻译：串行数据速率最高可达每秒10吉比特的减少信道信号数据丢失的方法包括将串行数据顺序地分配到多个编码器。单个数据字节从编码器发送到卷积交织器。每个字节在接收到的字节序列中分配给交织器的单独存储元件。地址生成器生成可分配给每个存储器元件的写入和读取地址。多个移位寄存器具有可变的刻度长度。串行数据分布在每个具有由移位寄存器长度差异产生的不同延迟元件的通道之间。延迟元件是可调整的，以纠正日常大气/通道变化造成的数据丢失。褪色检测信号在传输之前插入并在接收器处测量。衰减信号有助于创建擦除位以提高解码精度并调整交织器延迟参数。

2. 发明授权

US08407492B2 System and method of asynchronous logic power management 有权
标题翻译：异步逻辑电源管理系统与方法
公开(公告)号：US08407492B2
公开(公告)日：2013-03-26
申请号：US12687676
申请日：2010-01-14
申请人： Thomas H. Friddell
发明人： Thomas H. Friddell
IPC分类号： G06F1/00 , G06F1/26 , G06F15/00 , G06F9/46 , H04L7/00
CPC分类号： G06F1/3203 , G06F1/3228 , G06F1/3287 , G06F1/3296 , H03L7/08 , Y02D10/171 , Y02D10/172
摘要： Methods, apparatuses, and systems are disclosed to facilitate power management of asynchronous logic devices to operate asynchronous logic devices at a desired level of processing throughput with minimal power consumption. A plurality of completion signals is received from a processing circuit. Each of the plurality of completion signals identifies an associated operation has been completed by the processing circuit. A plurality of phase signals is generated where the plurality of phase signals includes a respective phase signal generated at a time when each of the plurality of completion signals is expected to be received. A plurality of time differences is determined where each of the time differences is based on a difference between receipt of a completion signal and the respective phase signal generated at the time when the completion signal is expected to be received. A composite difference of the time differences is totaled. A voltage supplied to the processing circuit is adjusted based on the composite difference.
摘要翻译：公开了方法，装置和系统，以促进异步逻辑器件的功率管理，以最小的功耗以期望的处理吞吐量水平操作异步逻辑器件。从处理电路接收多个完成信号。多个完成信号中的每一个识别相关联的操作已由处理电路完成。产生多个相位信号，其中多个相位信号包括在预期接收多个完成信号中的每一个时产生的相应相位信号。确定多个时间差，其中每个时间差基于完成信号的接收与期望接收完成信号时产生的各个相位信号之间的差异。时间差的复合差异总计。基于复合差异来调整提供给处理电路的电压。

3. 发明授权

US08127198B2 Adaptable channel compensation for reliable communication over fading communication links 有权
标题翻译：适应性信道补偿，用于通过衰落通信链路进行可靠的通信
公开(公告)号：US08127198B2
公开(公告)日：2012-02-28
申请号：US12115720
申请日：2008-05-06
申请人： Thomas H. Friddell
发明人： Thomas H. Friddell
IPC分类号： H03M13/00
CPC分类号： H03M13/2789 , H03M13/15 , H03M13/1515 , H03M13/2732 , H03M13/2936 , H03M13/2957 , H03M13/353 , H03M13/6508 , H03M13/6561 , H03M13/6566
摘要： A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.
摘要翻译：用于减少高达每秒大约10吉比特的串行数据速率的衰落信道信号数据丢失的方法包括将串行数据顺序地分配到多个编码器。单个数据字节从编码器发送到卷积交织器。每个字节在接收到的字节序列中分配给交织器的单独存储元件。地址生成器生成可分配给每个存储器元件的写入和读取地址。多个移位寄存器具有可变的刻度长度。串行数据分布在每个具有由移位寄存器长度差异产生的不同延迟元件的通道之间。延迟元件是可调整的，以纠正日常大气/通道变化造成的数据丢失。褪色检测信号在传输之前插入并在接收器处测量。衰减信号有助于创建擦除位以提高解码精度并调整交织器延迟参数。

4. 发明申请

US20110169543A1 SYSTEM AND METHOD OF CONTROLLING DEVICES OPERATING WITHIN DIFFERENT VOLTAGE RANGES 有权
标题翻译：控制在不同电压范围内运行的器件的系统和方法
公开(公告)号：US20110169543A1
公开(公告)日：2011-07-14
申请号：US12636875
申请日：2009-12-14
申请人： Thomas H. Friddell
发明人： Thomas H. Friddell
IPC分类号： H03L5/00
CPC分类号： H03K19/017509 , G06F1/3203 , G06F1/3287 , G06F1/3296 , Y02D10/171 , Y02D10/172
摘要： Semiconductor devices, systems, and methods are disclosed to facilitate power management. A semiconductor device includes a first voltage island configured to operate within a first voltage range, where the first voltage range has a first midpoint. A second voltage island of the semiconductor device is configured to operate within a second voltage range, where the second voltage range has a second midpoint. The first voltage range is different than the second voltage range, and the first midpoint is substantially equal to the second midpoint.
摘要翻译：公开了半导体器件，系统和方法以便于电源管理。半导体器件包括被配置为在第一电压范围内工作的第一电压岛，其中第一电压范围具有第一中点。半导体器件的第二电压岛被配置为在第二电压范围内工作，其中第二电压范围具有第二中点。第一电压范围不同于第二电压范围，第一中点基本上等于第二中点。

5. 发明申请

US20100283655A1 ACTIVE CHAFF 有权
标题翻译：活动CHAFF
公开(公告)号：US20100283655A1
公开(公告)日：2010-11-11
申请号：US12239434
申请日：2008-09-26
申请人： Michael J. Dunn , Brian Kenneth Kormanyos , Thomas H. Friddell
发明人： Michael J. Dunn , Brian Kenneth Kormanyos , Thomas H. Friddell
IPC分类号： H01Q15/00
CPC分类号： F42B12/382 , G01S7/38 , G01S7/495 , H01Q1/22 , H01Q1/28
摘要： An active chaff may be released by an aircraft to assist the aircraft in evading at least one of radar detection and a missile. The active chaff may include a signal generator, a signal spreading device, a microprocessor, a power source, and a substantially high-drag aerodynamic envelope. The signal generator may emit a signal to assist the aircraft in evading radar detection and/or a missile. The signal spreading device may spread the generated signal. The microprocessor may control the signal generator and the signal spreading device. The power source may power the signal generator and the microprocessor. Each of the signal generator, signal spreading device, microprocessor, and power source may be located on or within the substantially high-drag aerodynamic envelope.
摘要翻译：飞机可以释放一个活动的糠壳，以协助飞机逃避雷达检测和导弹中的至少一个。活动谷壳可以包括信号发生器，信号扩展装置，微处理器，电源和基本上高阻力的空气动力学外壳。信号发生器可以发出信号以帮助飞机逃避雷达检测和/或导弹。信号扩展装置可以扩展生成的信号。微处理器可以控制信号发生器和信号扩展装置。电源可以为信号发生器和微处理器供电。信号发生器，信号扩展装置，微处理器和电源中的每一个可以位于基本上高阻力的空气动力学外壳上或内部。

6. 发明授权

US08537048B2 Active chaff 有权
标题翻译：活动谷壳
公开(公告)号：US08537048B2
公开(公告)日：2013-09-17
申请号：US12239434
申请日：2008-09-26
申请人： Michael J. Dunn , Brian Kenneth Kormanyos , Thomas H. Friddell
发明人： Michael J. Dunn , Brian Kenneth Kormanyos , Thomas H. Friddell
IPC分类号： G01S7/38
CPC分类号： F42B12/382 , G01S7/38 , G01S7/495 , H01Q1/22 , H01Q1/28
摘要： An active chaff may be released by an aircraft to assist the aircraft in evading at least one of radar detection and a missile. The active chaff may include a signal generator, a signal spreading device, a microprocessor, a power source, and a substantially high-drag aerodynamic envelope. The signal generator may emit a signal to assist the aircraft in evading radar detection and/or a missile. The signal spreading device may spread the generated signal. The microprocessor may control the signal generator and the signal spreading device. The power source may power the signal generator and the microprocessor. Each of the signal generator, signal spreading device, microprocessor, and power source may be located on or within the substantially high-drag aerodynamic envelope.
摘要翻译：飞机可以释放一个活动的糠壳，以协助飞机逃避雷达检测和导弹中的至少一个。活动谷壳可以包括信号发生器，信号扩展装置，微处理器，电源和基本上高阻力的空气动力学外壳。信号发生器可以发出信号以帮助飞机逃避雷达检测和/或导弹。信号扩展装置可以扩展生成的信号。微处理器可以控制信号发生器和信号扩展装置。电源可以为信号发生器和微处理器供电。信号发生器，信号扩展装置，微处理器和电源中的每一个可以位于基本上高阻力的空气动力学外壳上或内部。

7. 发明申请

US20110169536A1 SYSTEM AND METHOD OF ASYNCHRONOUS LOGIC POWER MANAGEMENT 有权
标题翻译：异步逻辑电源管理系统与方法
公开(公告)号：US20110169536A1
公开(公告)日：2011-07-14
申请号：US12687676
申请日：2010-01-14
申请人： Thomas H. Friddell
发明人： Thomas H. Friddell
IPC分类号： H03L7/06
CPC分类号： G06F1/3203 , G06F1/3228 , G06F1/3287 , G06F1/3296 , H03L7/08 , Y02D10/171 , Y02D10/172
摘要： Methods, apparatuses, and systems are disclosed to facilitate power management of asynchronous logic devices to operate asynchronous logic devices at a desired level of processing throughput with minimal power consumption. A plurality of completion signals are received from a processing circuit. Each of the plurality of completion signals identifies an associated operation has been completed by the processing circuit. A plurality of phase signals is generated where the plurality of phase signals includes a respective phase signal generated at a time when each of the plurality of completion signals is expected to be received. A plurality of time differences is determined where each of the time differences is based on a difference between receipt of a completion signal and the respective phase signal generated at the time when the completion signal is expected to be received. A composite difference of the time differences is totaled. A voltage supplied to the processing circuit is adjusted based on the composite difference.
摘要翻译：公开了方法，装置和系统，以促进异步逻辑器件的功率管理，以最小的功耗以期望的处理吞吐量水平操作异步逻辑器件。从处理电路接收多个完成信号。多个完成信号中的每一个识别相关联的操作已由处理电路完成。产生多个相位信号，其中多个相位信号包括在预期接收多个完成信号中的每一个时产生的相应相位信号。确定多个时间差，其中每个时间差基于完成信号的接收与期望接收完成信号时产生的各个相位信号之间的差异。时间差的复合差异总计。基于复合差异来调整提供给处理电路的电压。

8. 发明授权

US08502590B2 System and method of controlling devices operating within different voltage ranges 有权
标题翻译：控制在不同电压范围内工作的设备的系统和方法
公开(公告)号：US08502590B2
公开(公告)日：2013-08-06
申请号：US12636875
申请日：2009-12-14
申请人： Thomas H. Friddell
发明人： Thomas H. Friddell
IPC分类号： H03L5/00
CPC分类号： H03K19/017509 , G06F1/3203 , G06F1/3287 , G06F1/3296 , Y02D10/171 , Y02D10/172
摘要： Semiconductor devices, systems, and methods are disclosed to facilitate power management. A semiconductor device includes a first voltage island configured to operate within a first voltage range, where the first voltage range has a first midpoint. A second voltage island of the semiconductor device is configured to operate within a second voltage range, where the second voltage range has a second midpoint. The first voltage range is different than the second voltage range, and the first midpoint is substantially equal to the second midpoint.
摘要翻译：公开了半导体器件，系统和方法以便于电源管理。半导体器件包括被配置为在第一电压范围内工作的第一电压岛，其中第一电压范围具有第一中点。半导体器件的第二电压岛被配置为在第二电压范围内工作，其中第二电压范围具有第二中点。第一电压范围不同于第二电压范围，第一中点基本上等于第二中点。

9. 发明授权

US07376882B2 Adaptable channel compensation for reliable communication over fading communication links 有权
标题翻译：适应性信道补偿，用于通过衰落通信链路进行可靠的通信
公开(公告)号：US07376882B2
公开(公告)日：2008-05-20
申请号：US11106093
申请日：2005-04-14
申请人： Thomas H Friddell
发明人： Thomas H Friddell
IPC分类号： H03M13/00
CPC分类号： H03M13/2789 , H03M13/15 , H03M13/1515 , H03M13/2732 , H03M13/2936 , H03M13/2957 , H03M13/353 , H03M13/6508 , H03M13/6561 , H03M13/6566
摘要： A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.
摘要翻译：用于减少高达每秒大约10吉比特的串行数据速率的衰落信道信号数据丢失的方法包括将串行数据顺序地分配到多个编码器。单个数据字节从编码器发送到卷积交织器。每个字节在接收到的字节序列中分配给交织器的单独存储元件。地址生成器生成可分配给每个存储器元件的写入和读取地址。多个移位寄存器具有可变的刻度长度。串行数据分布在每个具有由移位寄存器长度差异产生的不同延迟元件的通道之间。延迟元件是可调整的，以纠正日常大气/通道变化造成的数据丢失。褪色检测信号在传输之前插入并在接收器处测量。衰减信号有助于创建擦除位以提高解码精度并调整交织器延迟参数。

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