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1. 发明申请

US20130174658A1 IMBALANCE CORRECTION METHOD AND IMBALANCE CORRECTION AMOUNT CALCULATION DEVICE FOR ROTOR 有权
标题翻译：不平等校正方法和不平等校正量转子计算装置
公开(公告)号：US20130174658A1
公开(公告)日：2013-07-11
申请号：US13824259
申请日：2011-08-31
申请人： Nariyuki Kataoka , Tetsuya Koyama
发明人： Nariyuki Kataoka , Tetsuya Koyama
IPC分类号： G01M1/22
CPC分类号： G01M1/22 , G01M1/16 , G01M1/30
摘要： An imbalance correction method for correcting the imbalance of a rotor measures the vibration state of the rotor before temporary correction and the vibration state of the rotor after the temporary correction in a plurality of rotational speeds in order to make vibration values below the standard. An aggregation range of the tips of correction vectors for obtaining a vibration value which satisfies a vibration standard is calculated from vibration vectors in the rotational speeds. A real correction vector is selected from correction vectors having the tips in a region in which the aggregation ranges calculated for each of the rotational speeds overlap one another among a plurality of the correction vectors. A real correction amount and a real correction phase are set based on the real correction vector. The imbalance of the rotor is corrected based on the real correction amount and the real correction phase.
摘要翻译：用于校正转子不平衡的不平衡校正方法在暂时校正之后测量转子的振动状态和在多个转速中的临时校正之后的转子的振动状态，以使振动值低于标准。根据旋转速度的振动矢量计算用于获得满足振动标准的振动值的校正矢量的前端的聚集范围。从在多个校正矢量中的每个旋转速度计算的聚合范围彼此重叠的区域中具有尖端的校正矢量中选择实际校正矢量。基于实际校正矢量来设定实际的校正量和实际校正相位。基于实际校正量和实际校正相位来校正转子的不平衡。

2. 发明授权

US07989707B2 Chip embedded substrate and method of producing the same 有权
标题翻译：芯片嵌入式基板及其制造方法
公开(公告)号：US07989707B2
公开(公告)日：2011-08-02
申请号：US11815580
申请日：2006-12-12
申请人： Takaharu Yamano , Hajime Iizuka , Hideaki Sakaguchi , Toshio Kobayashi , Tadashi Arai , Tsuyoshi Kobayashi , Tetsuya Koyama , Kiyoaki Iida , Tomoaki Mashima , Koichi Tanaka , Yuji Kunimoto , Takashi Yanagisawa
发明人： Takaharu Yamano , Hajime Iizuka , Hideaki Sakaguchi , Toshio Kobayashi , Tadashi Arai , Tsuyoshi Kobayashi , Tetsuya Koyama , Kiyoaki Iida , Tomoaki Mashima , Koichi Tanaka , Yuji Kunimoto , Takashi Yanagisawa
IPC分类号： H05K1/16
CPC分类号： H01L23/5389 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/56 , H01L21/563 , H01L21/565 , H01L21/6835 , H01L23/3114 , H01L23/3121 , H01L23/3128 , H01L23/49822 , H01L23/49833 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/552 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/97 , H01L25/105 , H01L25/16 , H01L25/162 , H01L2221/68345 , H01L2224/0401 , H01L2224/1134 , H01L2224/13144 , H01L2224/16145 , H01L2224/16225 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81005 , H01L2224/81193 , H01L2224/81801 , H01L2224/83101 , H01L2224/83102 , H01L2224/83192 , H01L2224/85 , H01L2224/92125 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00012 , H01L2924/00014 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/07811 , H01L2924/12042 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/19105 , H01L2924/207 , H01L2924/3025 , H01L2924/3511 , H05K1/185 , H05K1/186 , H05K3/20 , H05K3/4614 , H05K3/462 , H05K3/4644 , H05K2201/10007 , H05K2201/10378 , H05K2201/10674 , H05K2201/10977 , Y10T29/4913 , Y10T29/49144 , Y10T29/49146 , H01L2924/00
摘要： A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.
摘要翻译：公开了一种制造芯片嵌入式基板的方法。该方法包括将半导体芯片安装在其上形成有第一布线的第一基板上的第一步骤; 以及将第一基板与形成有第二布线的第二基板接合的第二步骤。在第二步骤中，将半导体芯片封装在第一基板和第二基板之间，并且在第一布线和第二布线之间形成电连接，以形成连接到半导体芯片的多层布线。

3. 发明授权

US07772689B2 Semiconductor package with a conductive post and wiring pattern 有权
标题翻译：具有导电柱和布线图案的半导体封装
公开(公告)号：US07772689B2
公开(公告)日：2010-08-10
申请号：US11470432
申请日：2006-09-06
申请人： Tsuyoshi Kobayashi , Tetsuya Koyama , Takaharu Yamano
发明人： Tsuyoshi Kobayashi , Tetsuya Koyama , Takaharu Yamano
IPC分类号： H01L23/12 , H05K7/00
CPC分类号： H01L23/49827 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/45139 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2924/01049
摘要： It is configured to comprise a semiconductor chip 110, a resin member 106 for forming a cavity 109 in which this semiconductor chip 110 is installed, and wiring 105 constructed of pattern wiring 105b formed so as to be exposed to an upper surface 106b of this resin member 106 and also connected to the semiconductor chip 110 and a post part 105a in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to a lower surface 106a of the resin member 106.
摘要翻译：其构造为包括半导体芯片110，用于形成其中安装该半导体芯片110的空腔109的树脂构件106和由图案布线105b构成的布线105，其形成为暴露于该树脂的上表面106b 构件106，并且还连接到半导体芯片110和其中一端连接到图案布线105b的后部105a，并且另一端形成为暴露于树脂构件106的下表面106a。

4. 发明申请

US20080168652A1 Method of manufacturing a multilayer wiring board 失效
标题翻译：多层布线板的制造方法
公开(公告)号：US20080168652A1
公开(公告)日：2008-07-17
申请号：US12007040
申请日：2008-01-04
申请人： Tetsuya Koyama , Tsuyoshi Kobayashi , Hiroyuki Kato , Yoshihiro Machida
发明人： Tetsuya Koyama , Tsuyoshi Kobayashi , Hiroyuki Kato , Yoshihiro Machida
IPC分类号： H05K3/36 , H05K3/02 , H05K3/06 , H01R9/00
CPC分类号： H05K3/4614 , H05K3/462 , H05K3/4647 , H05K2203/061 , H05K2203/0733 , H05K2203/1327 , H05K2203/1476 , Y10T29/49124 , Y10T29/49126 , Y10T29/49146 , Y10T29/49147 , Y10T29/49155 , Y10T29/4916 , Y10T29/49165
摘要： First, a unilayer wiring board is fabricated, which has wiring layers formed in desired shapes on both sides of an insulating base member; and a metal bump formed on the wiring layer on one side of the insulating base member. Then, a desired number of unilayer boards are prepared and stacked up. On that case, the board disposed in the uppermost layer is prepared without having a metal bump. The boards are positioned and stacked up in such a manner that a metal bump of one of adjacent boards is connected to a corresponding wiring layer of the other board. Thereafter, resin is filled into gaps between the stacked boards, and insulating layers are formed on both sides of a multilayer board obtained through the above steps, in such a manner as to cover the entire surface except pad areas defined at predetermined positions on the wiring layers.
摘要翻译：首先，制造单层布线板，其具有在绝缘基材的两侧形成为所需形状的布线层; 以及在所述绝缘基体的一侧上的所述布线层上形成的金属凸块。然后，准备并堆叠所需数量的单层板。在这种情况下，准备设置在最上层的板，而不具有金属凸块。这些板被定位和堆叠，使得相邻板中的一个的金属凸块连接到另一个板的对应的布线层。此后，将树脂填充到堆叠板之间的间隙中，并且在通过上述步骤获得的多层板的两侧上形成绝缘层，以覆盖除了在布线上的预定位置限定的焊盘区域之外的整个表面层。

5. 发明申请

US20070052071A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US20070052071A1
公开(公告)日：2007-03-08
申请号：US11470432
申请日：2006-09-06
申请人： Tsuyoshi Kobayashi , Tetsuya Koyama , Takaharu Yamano
发明人： Tsuyoshi Kobayashi , Tetsuya Koyama , Takaharu Yamano
IPC分类号： H01L23/495
CPC分类号： H01L23/49827 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/45139 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2924/01049
摘要： It is configured to comprise a semiconductor chip 110, a resin member 106 for forming a cavity 109 in which this semiconductor chip 110 is installed, and wiring 105 constructed of pattern wiring 105b formed so as to be exposed to a lower surface 106a of this resin member 106 and also connected to the semiconductor chip 110 and a post part 105a in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to a front surface 106b of the resin member 106.
摘要翻译：其构造为包括半导体芯片110，用于形成其中安装该半导体芯片110的空腔109的树脂构件106和由图案布线105b构成的布线105，其形成为暴露于下表面106a 该树脂构件106还连接到半导体芯片110和其一端连接到图案布线105b的后部105a，并且另一端形成为暴露于前部表面106b 树脂构件106。

6. 发明授权

US08468851B2 Vacuum degassing apparatus and vacuum degassing method for molten glass 有权
公开(公告)号：US08468851B2
公开(公告)日：2013-06-25
申请号：US13600925
申请日：2012-08-31
申请人： Toru Nishikawa , Hironobu Yamamichi , Tetsuya Koyama , Yuji Endo , Hajime Itoh
发明人： Toru Nishikawa , Hironobu Yamamichi , Tetsuya Koyama , Yuji Endo , Hajime Itoh
IPC分类号： C03B5/225
CPC分类号： C03B5/2252 , Y02P40/57
摘要： A vacuum degassing apparatus for molten glass is comprised of an uprising pipe, a vacuum degassing vessel, a downfalling pipe, an upstream side pit that supplies molten glass to the uprising pipe, and a downstream side pit that receives molten glass from the downfalling pipe. The vacuum degassing apparatus for molten glass is further comprised of a separating mechanism that separates a part of molten glass moving from the downfalling pipe to the downstream side pit, and a returning pipe that returns separated molten glass to the upstream side pit.

7. 发明授权

US08347654B2 Vacuum degassing apparatus and vacuum degassing method for molten glass 有权
公开(公告)号：US08347654B2
公开(公告)日：2013-01-08
申请号：US12853408
申请日：2010-08-10
申请人： Toru Nishikawa , Hironobu Yamamichi , Tetsuya Koyama , Yuji Endo , Hajime Itoh
发明人： Toru Nishikawa , Hironobu Yamamichi , Tetsuya Koyama , Yuji Endo , Hajime Itoh
IPC分类号： C03B5/16
CPC分类号： C03B5/2252 , Y02P40/57
摘要： A vacuum degassing apparatus for molten glass is comprised of an uprising pipe, a vacuum degassing vessel, a downfalling pipe, an upstream side pit that supplies molten glass to the uprising pipe, and a downstream side pit that receives molten glass from the downfalling pipe. The vacuum degassing apparatus for molten glass is further comprised of a separating mechanism that separates a part of molten glass moving from the downfalling pipe to the downstream side pit, and a returning pipe that returns separated molten glass to the upstream side pit.

8. 发明授权

US08096049B2 Method of manufacturing a multilayer wiring board 失效
标题翻译：多层布线板的制造方法
公开(公告)号：US08096049B2
公开(公告)日：2012-01-17
申请号：US12929090
申请日：2010-12-30
申请人： Tetsuya Koyama , Tsuyoshi Kobayashi , Hiroyuki Kato , Yoshihiro Machida
发明人： Tetsuya Koyama , Tsuyoshi Kobayashi , Hiroyuki Kato , Yoshihiro Machida
IPC分类号： H01K3/00
CPC分类号： H05K3/4614 , H05K3/462 , H05K3/4647 , H05K2203/061 , H05K2203/0733 , H05K2203/1327 , H05K2203/1476 , Y10T29/49124 , Y10T29/49126 , Y10T29/49146 , Y10T29/49147 , Y10T29/49155 , Y10T29/4916 , Y10T29/49165
摘要： First, a unilayer wiring board is fabricated, which has wiring layers formed in desired shapes on both sides of an insulating base member; and a metal bump formed on the wiring layer on one side of the insulating base member. Then, a desired number of unilayer boards are prepared and stacked up. On that case, the board disposed in the uppermost layer is prepared without having a metal bump. The boards are positioned and stacked up in such a manner that a metal bump of one of adjacent boards is connected to a corresponding wiring layer of the other board. Thereafter, resin is filled into gaps between the stacked boards, and insulating layers are formed on both sides of a multilayer board obtained through the above steps, in such a manner as to cover the entire surface except pad areas defined at predetermined positions on the wiring layers.
摘要翻译：首先，制造单层布线板，其具有在绝缘基材的两侧形成为所需形状的布线层; 以及在所述绝缘基体的一侧上的所述布线层上形成的金属凸块。然后，准备并堆叠所需数量的单层板。在这种情况下，准备设置在最上层的板，而不具有金属凸块。这些板被定位和堆叠，使得相邻板中的一个的金属凸块连接到另一个板的对应的布线层。此后，将树脂填充到堆叠板之间的间隙中，并且在通过上述步骤获得的多层板的两侧上形成绝缘层，以覆盖除了在布线上的预定位置限定的焊盘区域之外的整个表面层。

9. 发明申请

US20070052083A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US20070052083A1
公开(公告)日：2007-03-08
申请号：US11465284
申请日：2006-08-17
申请人： Tsuyoshi Kobayashi , Tetsuya Koyama , Takaharu Yamano
发明人： Tsuyoshi Kobayashi , Tetsuya Koyama , Takaharu Yamano
IPC分类号： H01L23/02 , H01L21/00
CPC分类号： H01L21/6835 , H01L21/4846 , H01L23/3107 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/105 , H01L2221/68345 , H01L2224/32225 , H01L2224/45139 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83191 , H01L2225/1035 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18165 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/01049
摘要： A semiconductor package 100 is constructed of a semiconductor chip 110, a sealing resin 106 for sealing this semiconductor chip 110, and wiring 105 formed inside the sealing resin 106. And, the wiring 105 is constructed of pattern wiring 105b connected to the semiconductor chip 110 and also formed so as to be exposed to a lower surface 106b of the sealing resin 106, and a post part 105a formed so as to extend in a thickness direction of the sealing resin 106, the post part in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to an upper surface 106a of the sealing resin 106.
摘要翻译：半导体封装100由半导体芯片110，用于密封该半导体芯片110的密封树脂106和形成在密封树脂106内部的布线105构成。并且，布线105由连接到半导体芯片110的图案布线105b构成，并且还形成为暴露于密封树脂106的下表面106b，以及形成为在密封树脂106的厚度方向，其一端连接到图案布线105b的另一端形成为暴露于密封树脂106的上表面106a。

10. 发明申请

US20060208356A1 Wiring board and method of manufacturing the same 有权
标题翻译：接线板及其制造方法
公开(公告)号：US20060208356A1
公开(公告)日：2006-09-21
申请号：US11372916
申请日：2006-03-10
申请人： Takaharu Yamano , Masahiro Sunohara , Hajime Iizuka , Tetsuya Koyama
发明人： Takaharu Yamano , Masahiro Sunohara , Hajime Iizuka , Tetsuya Koyama
IPC分类号： H01L23/48
CPC分类号： H01L23/5383 , H01L21/563 , H01L21/6835 , H01L23/18 , H01L23/3128 , H01L23/49805 , H01L23/49816 , H01L23/5389 , H01L24/81 , H01L25/0655 , H01L2221/68345 , H01L2224/1134 , H01L2224/13144 , H01L2224/136 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/81191 , H01L2224/8121 , H01L2224/81815 , H01L2224/83102 , H01L2224/92125 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/381 , H05K1/185 , H05K3/4644 , Y10T29/49126 , Y10T29/4913 , Y10T29/49135 , Y10T29/49155 , Y10T29/49156 , H01L2224/13099 , H01L2924/00 , H01L2224/0401
摘要： A wiring board includes an insulating layer in which a semiconductor chip is embedded, and a wiring structure connected to the semiconductor chip. A reinforcing member reinforcing the insulating layer is embedded in the insulating layer. This enables reduction in a thickness of the wiring board and a suppression of warpage of the wiring board.
摘要翻译：布线基板包括嵌入有半导体芯片的绝缘层和与半导体芯片连接的布线结构。加强绝缘层的加强构件嵌入在绝缘层中。这样可以减少布线板的厚度和抑制布线板的翘曲。

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