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1. 发明申请

US20130203187A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20130203187A1
公开(公告)日：2013-08-08
申请号：US13827068
申请日：2013-03-14
申请人： Masamichi MATSUOKA , Tatsuya FUKUMURA
发明人： Masamichi MATSUOKA , Tatsuya FUKUMURA
IPC分类号： H01L43/02
CPC分类号： H01L43/02 , G11C11/161 , H01L27/228 , H01L43/08
摘要： The semiconductor device of this invention includes a semiconductor substrate having a main surface, and a magnetoresistive element located over the main surface of the semiconductor substrate. Further, it includes a protective layer, a wiring, a first upper electrode, and a second upper electrode. The protective layer is disposed so as to cover the side surface of the magnetoresistive element. The wiring is located over the top of the magnetoresistive element. The first upper electrode substantially the same in dimensions in plan view as the magnetoresistive element is disposed over the magnetoresistive element. The second upper electrode is electrically coupled with the first upper electrode over the first upper electrode, and larger in dimensions in plan view than the first upper electrode.
摘要翻译：本发明的半导体器件包括具有主表面的半导体衬底和位于半导体衬底的主表面上方的磁阻元件。此外，它包括保护层，布线，第一上电极和第二上电极。保护层设置成覆盖磁阻元件的侧表面。布线位于磁阻元件顶部的上方。当磁阻元件设置在磁阻元件上方时，第一上电极在平面图中的尺寸基本相同。第二上电极与第一上电极电连接在第一上电极上，并且在平面图中的尺寸大于第一上电极。

2. 发明授权

US07662686B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07662686B2
公开(公告)日：2010-02-16
申请号：US11936339
申请日：2007-11-07
申请人： Tatsuya Fukumura , Yoshihiro Ikeda , Shunichi Narumi , Izumi Takesue
发明人： Tatsuya Fukumura , Yoshihiro Ikeda , Shunichi Narumi , Izumi Takesue
IPC分类号： H01L21/336
CPC分类号： H01L27/11517 , G11C16/0433 , H01L21/32053 , H01L21/32055 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42376
摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
摘要翻译：具有非易失性存储器的半导体器件的尺寸减小。在具有多个非易失性存储单元的AND型闪速存储器中，具有多个第一电极，与之交叉的多个字线，以及设置在分别位于多个相邻的第一电极之间且重叠的位置的多个浮置栅电极如平面图所示，多个字线如横截面那样形成为凸形，从而高于第一电极。结果，即使非易失性存储单元的尺寸减小，也可以容易地处理浮置栅电极。此外，可以提高字线的浮栅电极和控制栅电极之间的耦合比，而不增加非易失存储单元所占的面积。

3. 发明授权

US07462905B2 Nonvolatile semiconductor memory device, semiconductor device and method of manufacturing nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件，半导体器件和制造非易失性半导体存储器件的方法
公开(公告)号：US07462905B2
公开(公告)日：2008-12-09
申请号：US11495455
申请日：2006-07-31
申请人： Yutaka Imai , Tatsuya Fukumura , Toshiaki Omori , Yutaka Takeshima
发明人： Yutaka Imai , Tatsuya Fukumura , Toshiaki Omori , Yutaka Takeshima
IPC分类号： H01L29/788 , H01L21/8239 , H01L23/528
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/764 , H01L27/11521
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, a first floating gate formed on a main surface of the semiconductor substrate, a second floating gate formed on the main surface of the semiconductor substrate, a first control gate formed on the first floating gate, a second control gate formed on the second floating gate, an interlayer insulating film, and a gap formed in the interlayer insulating film in at least a portion located between the first and second floating gates. Accordingly, a nonvolatile semiconductor memory device for which variations in threshold voltage of a memory cell can be suppressed and an appropriate read operation can be carried out, as well as a method of manufacturing the nonvolatile semiconductor memory device are provided. Further, a capacitance formed between interconnect lines can be reduced and the drive speed can be improved.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的主表面上的第一浮置栅极，形成在半导体衬底的主表面上的第二浮置栅极，形成在第一浮动栅极上的第一控制栅极，形成在第二浮栅上的第二控制栅极，层间绝缘膜，以及形成在位于第一和第二浮栅之间的至少一部分的层间绝缘膜中的间隙。因此，提供了可以抑制存储单元的阈值电压的变化并且可以执行适当的读取操作的非易失性半导体存储器件以及制造非易失性半导体存储器件的方法。此外，可以降低在互连线之间形成的电容，并且可以提高驱动速度。

4. 发明申请

US20060022257A1 Semiconductor device and a method of manufacturing the same 有权
公开(公告)号：US20060022257A1
公开(公告)日：2006-02-02
申请号：US11240375
申请日：2005-10-03
申请人： Tatsuya Fukumura , Yoshihiro Ikeda , Shunichi Narumi , Izumi Takesue
发明人： Tatsuya Fukumura , Yoshihiro Ikeda , Shunichi Narumi , Izumi Takesue
IPC分类号： H01L29/788
CPC分类号： H01L27/11517 , G11C16/0433 , H01L21/32053 , H01L21/32055 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42376
摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.

5. 发明申请

US20110121419A1 METHOD FOR MANUFACTURING A MAGNETIC MEMORY DEVICE AND MAGNETIC MEMORY DEVICE 审中-公开
标题翻译：用于制造磁记录装置和磁记忆装置的方法
公开(公告)号：US20110121419A1
公开(公告)日：2011-05-26
申请号：US13021079
申请日：2011-02-04
申请人： Shuichi UENO , Haruo Furuta , Ryoji Matsuda , Tatsuya Fukumura , Shin Hasegawa , Shinya Hirano , Hiroyuki Chibahara , Hiroshi Oshita
发明人： Shuichi UENO , Haruo Furuta , Ryoji Matsuda , Tatsuya Fukumura , Shin Hasegawa , Shinya Hirano , Hiroyuki Chibahara , Hiroshi Oshita
IPC分类号： H01L29/82
CPC分类号： H01L43/12 , G11C11/161 , G11C11/1659 , G11C11/1675 , H01L27/228
摘要： A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.
摘要翻译：一种制造包括TMR元件的磁存储器件的方法，所述方法包括：形成下布线层的步骤; 在下布线层上形成层间绝缘层的步骤; 在所述层间绝缘层中形成开口以使所述下部布线层露出的步骤; 形成阻挡金属层以使得层间绝缘层和开口的内表面被覆盖的步骤; 在所述阻挡金属层上形成金属层以使得所述开口嵌入的步骤; 抛光步骤，通过使用阻挡金属层作为阻挡层进行研磨来去除阻挡金属层上的金属层，使得形成包含金属层的布线层嵌入开口和阻挡金属层中; 以及在所述布线层上制造TMR元件的元件制造步骤。

6. 发明申请

US20060033141A1 Method of manufacturing a semiconductor device having trenches for isolation and capacitor 审中-公开
标题翻译：制造具有用于隔离和电容器的沟槽的半导体器件的方法
公开(公告)号：US20060033141A1
公开(公告)日：2006-02-16
申请号：US11248309
申请日：2005-10-13
申请人： Tsutomu Okazaki , Daisuke Okada , Yoshihiro Ikeda , Keisuke Tsukamoto , Tatsuya Fukumura , Shoji Shukuri , Keiichi Haraguchi , Koji Kishi
发明人： Tsutomu Okazaki , Daisuke Okada , Yoshihiro Ikeda , Keisuke Tsukamoto , Tatsuya Fukumura , Shoji Shukuri , Keiichi Haraguchi , Koji Kishi
IPC分类号： H01L29/94 , H01L21/383
CPC分类号： H01L27/11536 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L29/66181 , H01L29/7833
摘要： At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor is increased, which enables improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench that are formed in the surface of the semiconductor substrate by the same step, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage insulating film in a MISFET formation region are formed by the same step; alternatively, the dielectric of the capacitor in the capacitor formation region and a memory gate interlayer film between a polysilicon layer and a polysilicon layer in the memory cell formation region are formed by the same step.
摘要翻译：在电容器形成区域的表面上形成至少不少于一个形成凹凸表面的电容器形成沟槽。因此，电容器的表面积增大，能够提高电容器的电容量，能够提高单位面积的电容器的电容。此外，通过形成通过相同的步骤形成在半导体衬底的表面中的电容器形成沟槽和元件形成沟槽，可以简化制造工艺。而通过相同的步骤形成电容器形成区域中的电容器的电介质膜和MISFET形成区域中的高压绝缘膜; 或者，电容器形成区域中的电容器的电介质和存储单元形成区域中的多晶硅层和多晶硅层之间的存储器栅极层间膜通过相同的步骤形成。

7. 发明申请

US20120068282A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120068282A1
公开(公告)日：2012-03-22
申请号：US13188888
申请日：2011-07-22
申请人： Masamichi MATSUOKA , Tatsuya Fukumura , Fumihiko Nitta
发明人： Masamichi MATSUOKA , Tatsuya Fukumura , Fumihiko Nitta
IPC分类号： H01L29/82 , H01L21/8246
CPC分类号： H01L27/228 , G11C11/161
摘要： To provide a semiconductor device capable of suppressing a short circuit between an upper conductive element and a lower conductive element which constitute an MRAM, and a manufacturing method of the same.There are provided a semiconductor substrate having a main surface, a magnetic tunnel junction structure located over the main surface of the semiconductor substrate and including a pin layer, a tunnel insulating layer, and a free layer, a lower insulating layer contacting a lower side surface of the magnetic tunnel junction structure, a sidewall insulating layer located over the lower insulating layer in contact with the upper side surface of the magnetic tunnel junction structure, and exposing the top surface of the magnetic tunnel junction structure, and a conductive layer contacting the top surface of the magnetic tunnel junction structure exposed from the sidewall insulating layer.
摘要翻译：提供能够抑制构成MRAM的上导电元件和下导电元件之间的短路的半导体器件及其制造方法。提供了一种具有主表面的半导体衬底，位于半导体衬底的主表面上方的磁性隧道结结构，并且包括引脚层，隧道绝缘层和自由层，下绝缘层与下表面接触的磁性隧道结结构的侧壁绝缘层，位于与所述磁性隧道结结构的上侧表面接触的所述下部绝缘层之上的侧壁绝缘层，以及暴露所述磁性隧道结结构的顶表面，以及与所述顶部从侧壁绝缘层暴露的磁性隧道结结构的表面。

8. 发明申请

US20110198715A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20110198715A1
公开(公告)日：2011-08-18
申请号：US13023188
申请日：2011-02-08
申请人： Masamichi MATSUOKA , Tatsuya Fukumura
发明人： Masamichi MATSUOKA , Tatsuya Fukumura
IPC分类号： H01L29/82 , H01L21/8246
CPC分类号： H01L43/02 , G11C11/161 , H01L27/228 , H01L43/08
摘要： The semiconductor device of this invention includes a semiconductor substrate having a main surface, and a magnetoresistive element located over the main surface of the semiconductor substrate. Further, it includes a protective layer, a wiring, a first upper electrode, and a second upper electrode. The protective layer is disposed so as to cover the side surface of the magnetoresistive element. The wiring is located over the top of the magnetoresistive element. The first upper electrode substantially the same in dimensions in plan view as the magnetoresistive element is disposed over the magnetoresistive element. The second upper electrode is electrically coupled with the first upper electrode over the first upper electrode, and larger in dimensions in plan view than the first upper electrode.
摘要翻译：本发明的半导体器件包括具有主表面的半导体衬底和位于半导体衬底的主表面上方的磁阻元件。此外，它包括保护层，布线，第一上电极和第二上电极。保护层设置成覆盖磁阻元件的侧表面。布线位于磁阻元件顶部的上方。当磁阻元件设置在磁阻元件上方时，第一上电极在平面图中的尺寸基本相同。第二上电极与第一上电极电连接在第一上电极上，并且在平面图中的尺寸大于第一上电极。

9. 发明申请

US20100084701A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100084701A1
公开(公告)日：2010-04-08
申请号：US12633815
申请日：2009-12-09
申请人： Tatsuya FUKUMURA , Yoshihiro Ikeda , Shunichi Narumi , Izumi Takesue
发明人： Tatsuya FUKUMURA , Yoshihiro Ikeda , Shunichi Narumi , Izumi Takesue
IPC分类号： H01L27/115
CPC分类号： H01L27/11517 , G11C16/0433 , H01L21/32053 , H01L21/32055 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42376
摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
摘要翻译：具有非易失性存储器的半导体器件的尺寸减小。在具有多个非易失性存储单元的AND型闪速存储器中，具有多个第一电极，与之交叉的多个字线，以及设置在分别位于多个相邻的第一电极之间且重叠的位置的多个浮置栅电极如平面图所示，多个字线如横截面那样形成为凸形，从而高于第一电极。结果，即使非易失性存储单元的尺寸减小，也可以容易地处理浮置栅电极。此外，可以提高字线的浮栅电极和控制栅电极之间的耦合比，而不增加非易失存储单元所占的面积。

10. 发明授权

US07312123B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07312123B2
公开(公告)日：2007-12-25
申请号：US11240375
申请日：2005-10-03
申请人： Tatsuya Fukumura , Yoshihiro Ikeda , Shunichi Narumi , Izumi Takesue
发明人： Tatsuya Fukumura , Yoshihiro Ikeda , Shunichi Narumi , Izumi Takesue
IPC分类号： H01L21/336
CPC分类号： H01L27/11517 , G11C16/0433 , H01L21/32053 , H01L21/32055 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42376
摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
摘要翻译：具有非易失性存储器的半导体器件的尺寸减小。在具有多个非易失性存储单元的AND型闪速存储器中，具有多个第一电极，与之交叉的多个字线，以及设置在分别位于多个相邻的第一电极之间且重叠的位置的多个浮栅电极如平面图所示，多个字线如横截面那样形成为凸形，从而高于第一电极。结果，即使非易失性存储单元的尺寸减小，也可以容易地处理浮置栅电极。此外，可以提高字线的浮栅电极和控制栅电极之间的耦合比，而不增加非易失存储单元所占的面积。

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