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1. 发明申请

US20070123415A1 Process for production of mesoporous structures 审中-公开
标题翻译：介孔结构的生产工艺
公开(公告)号：US20070123415A1
公开(公告)日：2007-05-31
申请号：US11602708
申请日：2006-11-21
申请人： Hiroaki Yotoh , Miho Ito , Takumi Okamoto
发明人： Hiroaki Yotoh , Miho Ito , Takumi Okamoto
IPC分类号： B01J23/10
CPC分类号： B01J29/041 , B01J23/10 , B01J29/0308 , C01B37/02
摘要： A process for production of a mesoporous structure wherein fine particles having a mean particle size smaller than the size of pores of a mesoporous body formed using a template are formed in the pores of the mesoporous body. The process comprises the steps of: preparing an aqueous solution comprising a mixture of the template and the fine particles, heating and pressurizing the aqueous solution to bring the water in the aqueous solution to a subcritical water state, returning the aqueous solution to a state at a room temperature and under atmospheric pressure, dissolving the starting material of the mesoporous body in the aqueous solution and heating it to form a precipitate comprising the template, fine particles and starting material of the mesoporous body, and separating, drying and firing the precipitate to burn off the template from the precipitate.
摘要翻译：在中孔体的孔中形成介孔结构体的制造方法，其中在介孔体的孔中形成平均粒径小于使用模板形成的介孔体的孔的尺寸的微粒。该方法包括以下步骤：制备包含模板和细颗粒的混合物的水溶液，加热和加压水溶液使水在水溶液中达到亚临界水状态，使水溶液返回到在室温和大气压下，将介孔体的原料溶解在水溶液中并加热，形成包含该介孔体的模板，细颗粒和原料的沉淀物，并将沉淀物分离，干燥和烧制从沉淀物中烧掉模板。

2. 发明授权

US08341579B2 Method, apparatus, and system for analyzing operation of semiconductor integrated circuits 失效
标题翻译：用于分析半导体集成电路的操作的方法，装置和系统
公开(公告)号：US08341579B2
公开(公告)日：2012-12-25
申请号：US13062263
申请日：2009-10-27
申请人： Takumi Okamoto , Takeshi Watanabe , Itsuki Yamada , Naoshi Doi , Tsuneo Tsukagoshi
发明人： Takumi Okamoto , Takeshi Watanabe , Itsuki Yamada , Naoshi Doi , Tsuneo Tsukagoshi
IPC分类号： G06F17/50
CPC分类号： G01R31/2848 , G06F17/5036
摘要： An operation analyzing apparatus (100) for semiconductor integrated circuits according to this exemplary embodiment includes a simulation analyzing unit (140), and the simulation analyzing unit (140) includes: a semiconductor characteristics extracting unit (110) that extracts the inductances L, resistances R, and capacitances C of a board, a package, and a semiconductor integrated circuit, from the semiconductor integrated circuit mounted on the board via the package; an individual network generating unit (111) that generates individual networks of the extracted inductance L, resistance R, and capacitance C with respect to each of said semiconductor substrate, said package, and said semiconductor integrated circuit; an integrated network generating unit (112) that generates an integrated network by integrating all of the generated individual networks; and an operation simulation running unit (113) that performs an operation simulation of the semiconductor integrated circuit by inserting a test noise pattern to an arbitrary position in the generated integrated network.
摘要翻译：根据本实施方式的半导体集成电路的动作分析装置（100）具有模拟分析部（140），所述模拟分析部（140）具备：提取电感L，电阻 R和电容C，从安装在板上的半导体集成电路经由封装形成的板，封装和半导体集成电路; 单个网络生成单元（111），其针对所述半导体衬底，所述封装和所述半导体集成电路中的每一个产生提取的电感L，电阻R和电容C的各个网络; 集成网络生成单元（112），其通过集成所有生成的各个网络来生成集成网络; 以及通过将测试噪声模式插入到所生成的集成网络中的任意位置来执行半导体集成电路的操作模拟的操作模拟运行单元（113）。

3. 发明申请

US20090288054A1 Method and apparatus for hierarchical design of semiconductor integrated circuit 失效
标题翻译：半导体集成电路分级设计方法及装置
公开(公告)号：US20090288054A1
公开(公告)日：2009-11-19
申请号：US12309038
申请日：2007-07-05
申请人： Takumi Okamoto
发明人： Takumi Okamoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0203
摘要： A hierarchical design apparatus 1 for a semiconductor integrated circuit includes a hierarchical block placing unit 1-02 which places sets of hierarchical blocks onto a chip; a hierarchical block terminal placing unit 1-03 which places terminals of the hierarchical blocks so that for sets of hierarchical blocks having the same function, the hierarchical blocks coincide with each other in a coordinate of the corresponding terminal; an intra-hierarchical block layout unit 1-06 which executes the individual types of intra-hierarchical-block layout designs, meanwhile executes only a single type of intra-hierarchical-block layout design for the sets of hierarchical blocks having the same function; and a chip layout finishing unit 1-07 which replicates thus-obtained layout patterns, and thereby completing a layout design over the entire chip.
摘要翻译：用于半导体集成电路的分层设计装置1包括：将分层块集合放置在芯片上的分层块放置单元1-02; 分级块终端放置单元1-03，其将分级块的终端设置为使得对于具有相同功能的分层块的集合，分层块在相应终端的坐标中彼此一致; 执行各种类型的层内块布局设计的层内块布局单元1-06，同时仅对具有相同功能的分层块集合执行单一类型的层内块布局设计; 以及复制由此获得的布局图案的芯片布局整理单元1-07，从而在整个芯片上完成布局设计。

4. 发明申请

US20090005576A1 Production Method of Optically Active Cyclohexane Ether Compounds 审中-公开
标题翻译：光活性环己烷醚化合物的制备方法
公开(公告)号：US20090005576A1
公开(公告)日：2009-01-01
申请号：US11813809
申请日：2006-01-12
申请人： Koji Machiya , Kazuo Ike , Masaru Watanabe , Toshitaka Yoshino , Takumi Okamoto , Yasuhiro Morinaga , Shoji Mizobata
发明人： Koji Machiya , Kazuo Ike , Masaru Watanabe , Toshitaka Yoshino , Takumi Okamoto , Yasuhiro Morinaga , Shoji Mizobata
IPC分类号： C07D207/12
CPC分类号： C07D207/12
摘要： The present invention relates to an industrial synthetic method of an optically active cyclohexane ether compound (IIIa) or a salt thereof, which is useful as a pharmaceutical agent, and an intermediate useful for the production method of the present invention. The production method of the present invention is as shown below: wherein each symbol is as defined in the specification. According to the production method of the present invention, efficient and stable supply of an optically active cyclohexane ether compound (IIIa) in a high yield at a lower cost can be afforded. Therefore, an optically active cyclohexane ether compound (IIIa) extremely useful as a pharmaceutical agent can be provided by an industrially highly advantageous method.
摘要翻译：本发明涉及可用作药剂的光学活性环己烷醚化合物（IIIa）或其盐的工业合成方法和可用于本发明的制备方法的中间体。本发明的制造方法如下所示：其中各符号如说明书中所定义。根据本发明的制造方法，能够以较低的成本高效稳定地供给光学活性的环己烷醚化合物（IIIa）。因此，通过工业上非常有利的方法可以提供作为药剂非常有用的光学活性的环己烷醚化合物（IIIa）。

5. 发明申请

US20140335174A1 DRY-COATED TABLET CONTAINING TEGAFUR, GIMERACIL AND OTERACIL POTASSIUM 审中-公开
标题翻译：含有TEGAFUR，GIMERACIL和OTERACIL POTASSIUM的干燥涂层
公开(公告)号：US20140335174A1
公开(公告)日：2014-11-13
申请号：US14118952
申请日：2012-05-24
申请人： Takumi Okamoto , Takashi Yoshizawa , Yoshito Ohnishi
发明人： Takumi Okamoto , Takashi Yoshizawa , Yoshito Ohnishi
IPC分类号： A61K9/28 , A61K31/4412 , A61K31/513 , A61K31/53
CPC分类号： A61K9/2866 , A61K9/0056 , A61K9/2826 , A61K9/284 , A61K9/286 , A61K9/2893 , A61K31/4412 , A61K31/513 , A61K31/53 , A61K2300/00
摘要： The present invention provides a dry-coated tablet comprising: an inner core containing, as active ingredients, (a) tegafur, (b) gimeracil, and (c) oteracil potassium; and an outer shell.
摘要翻译：本发明提供一种干包衣片剂，其包含：含有作为活性成分的（a）替加氟，（b）吉美脯氨酸和（c）奥替卡尔钾的内核; 和外壳。

6. 发明授权

US08141022B2 Method and apparatus for hierarchical design of semiconductor integrated circuit 失效
标题翻译：半导体集成电路分级设计方法及装置
公开(公告)号：US08141022B2
公开(公告)日：2012-03-20
申请号：US12309038
申请日：2007-07-05
申请人： Takumi Okamoto
发明人： Takumi Okamoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0203
摘要： A hierarchical design apparatus 1 for a semiconductor integrated circuit includes a hierarchical block placing unit 1-02 which places sets of hierarchical blocks onto a chip; a hierarchical block terminal placing unit 1-03 which places terminals of the hierarchical blocks so that for sets of hierarchical blocks having the same function, the hierarchical blocks coincide with each other in a coordinate of the corresponding terminal; an intra-hierarchical block layout unit 1-06 which executes the individual types of intra-hierarchical-block layout designs, meanwhile executes only a single type of intra-hierarchical-block layout design for the sets of hierarchical blocks having the same function; and a chip layout finishing unit 1-07 which replicates thus-obtained layout patterns, and thereby completing a layout design over the entire chip.
摘要翻译：用于半导体集成电路的分层设计装置1包括：将分层块集合放置在芯片上的分层块放置单元1-02; 分级块终端放置单元1-03，其将分级块的终端设置为使得对于具有相同功能的分层块的集合，分层块在相应终端的坐标中彼此一致; 执行各种类型的层内块布局设计的层内块布局单元1-06，同时仅对具有相同功能的分层块集合执行单一类型的层内块布局设计; 以及复制由此获得的布局图案的芯片布局整理单元1-07，从而在整个芯片上完成布局设计。

7. 发明申请

US20110296369A1 OPERATION ANALYZING METHOD, OPERATION ANALYZING APPARATUS, OPERATION ANALYZING PROGRAM, AND OPERATION ANALYZING SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUITS 失效
标题翻译：操作分析方法，操作分析设备，操作分析程序和半导体集成电路操作分析系统
公开(公告)号：US20110296369A1
公开(公告)日：2011-12-01
申请号：US13062263
申请日：2009-10-27
申请人： Takumi Okamoto , Takeshi Watanabe , Itsuki Yamada , Naoshi Doi , Tsuneo Tsukagoshi
发明人： Takumi Okamoto , Takeshi Watanabe , Itsuki Yamada , Naoshi Doi , Tsuneo Tsukagoshi
IPC分类号： G06F11/22
CPC分类号： G01R31/2848 , G06F17/5036
摘要： An operation analyzing apparatus (100) for semiconductor integrated circuits according to this exemplary embodiment includes a simulation analyzing unit (140), and the simulation analyzing unit (140) includes: a semiconductor characteristics extracting unit (110) that extracts the inductances L, resistances R, and capacitances C of a board, a package, and a semiconductor integrated circuit, from the semiconductor integrated circuit mounted on the board via the package; an individual network generating unit (111) that generates individual networks of the extracted inductance L, resistance R, and capacitance C with respect to each of said semiconductor substrate, said package, and said semiconductor integrated circuit; an integrated network generating unit (112) that generates an integrated network by integrating all of the generated individual networks; and an operation simulation running unit (113) that performs an operation simulation of the semiconductor integrated circuit by inserting a test noise pattern to an arbitrary position in the generated integrated network.
摘要翻译：根据本实施方式的半导体集成电路的动作分析装置（100）具有模拟分析部（140），所述模拟分析部（140）具备：提取电感L，电阻 R和电容C，从安装在板上的半导体集成电路经由封装形成的板，封装和半导体集成电路; 单个网络生成单元（111），其针对所述半导体衬底，所述封装和所述半导体集成电路中的每一个产生提取的电感L，电阻R和电容C的各个网络; 集成网络生成单元（112），其通过集成所有生成的各个网络来生成集成网络; 以及通过将测试噪声模式插入到所生成的集成网络中的任意位置来执行半导体集成电路的操作模拟的操作模拟运行单元（113）。

8. 发明授权

US06391915B2 Propanolamine derivatives 失效
标题翻译：丙醇胺衍生物
公开(公告)号：US06391915B2
公开(公告)日：2002-05-21
申请号：US09380608
申请日：1999-09-15
申请人： Kiyoshi Taniguchi , Minoru Sakurai , Norio Hashimoto , Takumi Okamoto , Kazunori Tsubaki , Yasuyo Tomishima , Hisashi Takasugi
发明人： Kiyoshi Taniguchi , Minoru Sakurai , Norio Hashimoto , Takumi Okamoto , Kazunori Tsubaki , Yasuyo Tomishima , Hisashi Takasugi
IPC分类号： A01N3712
CPC分类号： C07C215/64 , C07C217/30 , C07C217/34 , C07C217/74 , C07C2602/10 , C07C2602/12 , Y02P20/55
摘要： This invention relates to new propanolamine derivatives presented by the following formula [I]: wherein R1 hydrogen or lower alkenyloxy, R2 is carboxy(lower)alkoxy or protected carboxy(lower)alkoxy, R3 is hydrogen or N-protective group, n is an integer of 1 or 2, and salts thereof which have gut selective sympathomimetic, anti-ulcerous, anti-pancreatitis, lipolytic and anti-pollakisuria activities, to processes for the preparation thereof and to a pharmaceutical composition comprising the same.
摘要翻译：本发明涉及由下式[I]表示的新的丙醇胺衍生物：其中R 1为氢或低级烯氧基，R 2为羧基（低级）烷氧基或保护的羧基（低级）烷氧基，R 3为氢或N-保护基，n为 1或2的整数及其盐，其具有肠选择性交感神经兴奋剂，抗溃疡性，抗胰腺炎，脂肪分解和抗花粉病活性，其制备方法和包含其的药物组合物。

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