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1. 发明授权

US06455882B1 Semiconductor device having a hydrogen barrier layer 失效
标题翻译：具有氢阻挡层的半导体器件
公开(公告)号：US06455882B1
公开(公告)日：2002-09-24
申请号：US09605385
申请日：2000-06-28
申请人： Takeshi Nakura
发明人： Takeshi Nakura
IPC分类号： H01L27108
CPC分类号： H01L28/55 , H01L21/3144 , H01L27/1085 , H01L27/10894
摘要： A consolidated LSI including a logic circuit section and a FeRAM section formed on a single chip has a hydrogen barrier layer covering the cell array of the FeRAM section. The hydrogen barrier layer is made of plasma CVD SiON and has an excellent hydrogen barrier function. The hydrogen barrier layer protects the ferroelectric film of a ferroelectric capacitor an against the hydrogen-annealing process in the fabrication a process for the consolidated LSI.
摘要翻译：包括形成在单个芯片上的逻辑电路部分和FeRAM部分的合并LSI具有覆盖FeRAM部分的电池阵列的氢阻挡层。氢阻挡层由等离子体CVD SiON制成，具有优异的氢屏障功能。在制造合并的LSI的工艺中，氢阻挡层保护铁电电容器的铁电体膜抵抗氢退火工艺。

2. 发明授权

US06836428B2 Semiconductor memory device including Shadow RAM 失效
标题翻译：半导体存储器件包括Shadow RAM
公开(公告)号：US06836428B2
公开(公告)日：2004-12-28
申请号：US10232672
申请日：2002-09-03
申请人： Takeshi Nakura , Tohru Miwa
发明人： Takeshi Nakura , Tohru Miwa
IPC分类号： G11C1400
CPC分类号： G11C14/00
摘要： There is provided a semiconductor memory device for preventing an increase of a cell area of a Shadow RAM comprising a portion of an SRAM memory cell and a ferroelectric capacitor connected to a storage node of the portion of the SRAM memory cell and achieving high capacitance formation of a storage capacitor. The Shadow RAM is provided with a relay wiring layer between a wiring layer corresponding to the storage node and a lower electrode of the ferroelectric capacitor, a wiring corresponding to the storage node is connected to a relay wiring via a first and a second opening portion arranged at a first interval and the lower electrode of the ferroelectric capacitor is connected to a relay wiring via a third and a fourth opening portion arranged at a second interval narrower than the first interval.
摘要翻译：提供了一种半导体存储器件，用于防止包括SRAM存储单元的一部分和连接到SRAM存储单元部分的存储节点的铁电电容器的阴影RAM的单元面积的增加，并实现高电容形成存储电容器。阴影RAM在与存储节点对应的布线层和铁电电容器的下电极之间设置有中继布线层，对应于存储节点的布线经由布置在第一和第二开口部的中继布线连接，并且所述强电介质电容器的下部电极经由第三开口部和第四开口部连接到中继配线，所述第三开口部和所述第四开口部配置成比所述第一间隔窄的第二间隔。

3. 发明授权

US06534358B2 Method of fabricating semiconductor device having ferroelectric capacitor 失效
标题翻译：制造具有铁电电容器的半导体器件的方法
公开(公告)号：US06534358B2
公开(公告)日：2003-03-18
申请号：US09838186
申请日：2001-04-20
申请人： Takeshi Nakura , Hidemitsu Mori , Seiichi Takahashi
发明人： Takeshi Nakura , Hidemitsu Mori , Seiichi Takahashi
IPC分类号： H01L218242
CPC分类号： H01L28/55 , H01L21/3105 , H01L27/10855 , H01L27/10894
摘要： An interlayer insulating film, contacts, and wirings are formed on a MOS transistor formed on a silicon substrate. Another interlayer insulating film and contacts are formed thereon. Subsequently, as a first heat treatment, a heat treatment is performed in a hydrogen atmosphere or a nitrogen- or otherwise-diluted hydrogen atmosphere at a temperature of the order of 300-500° C. for about 5-60 minutes, thereby recovering defects that occur in the MOS transistor and insulating film forming steps and the like. Then, a ferroelectric capacitor connected to either diffusion layer of the MOS transistor is formed along with wirings, electrodes, and the like. Thereafter, as a second heat treatment, a heat treatment is performed in nitrogen at a temperature of the order of 300-500° C. for about 5-60 minutes. This recovers defects that occur after the first heat treatment step.
摘要翻译：在形成于硅衬底上的MOS晶体管上形成层间绝缘膜，触点和布线。在其上形成另一层间绝缘膜和触点。随后，作为第一热处理，在氢气氛或氮气或其它稀释的氢气氛中，在约300-500℃的温度下进行约5-60分钟的热处理，从而回收缺陷发生在MOS晶体管和绝缘膜形成步骤等中。然后，连接到MOS晶体管的任一扩散层的铁电电容器与布线，电极等一起形成。此后，作为第二热处理，在氮气中在约300-500℃的温度下进行约5-60分钟的热处理。这恢复了在第一热处理步骤之后发生的缺陷。

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