专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08833150B2 Apparatus and method for detecting abnormality of imbalance of air-fuel ratios among cylinders 有权
标题翻译：检测气缸间空燃比不平衡异常的装置及方法
公开(公告)号：US08833150B2
公开(公告)日：2014-09-16
申请号：US13687910
申请日：2012-11-28
申请人： Takashi Yui , Kota Hayashi , Tokiji Ito
发明人： Takashi Yui , Kota Hayashi , Tokiji Ito
IPC分类号： G01M15/10 , G01M15/04
CPC分类号： G01M15/042 , Y02T10/40
摘要： A detecting apparatus that detects an abnormality of imbalance of air-fuel ratios among cylinders of a multi-cylinder internal combustion engine, which is equipped with a variable working angle mechanism of an intake valve, the detecting apparatus includes an abnormality detection portion that detects a parameter regarding rotational fluctuations of each of the cylinders and detects whether or not there is an abnormality of imbalance of air-fuel ratios among the cylinders. The abnormality detection portion refrains from determining that the air-fuel ratios are normal when the working angle at the time of detection of the parameter is within a predetermined large working angle range, and determines that the air-fuel ratios are normal when the working angle at the time of detection of the parameter is within a predetermined small working angle range that is on a small working angle side with respect to the large working angle range.
摘要翻译：一种检测装置，其检测配备有进气门的可变作用角机构的多缸内燃机的气缸之间的空燃比的不平衡的异常的检测装置，所述检测装置包括：异常检测部，其检测参数关于每个气缸的旋转波动，并且检测气缸之间是否存在空燃比不平衡的异常。当检测到参数时的工作角度在预定的大的工作角度范围内时，异常检测部分不能确定空燃比是正常的，并且当工作角度在检测到参数的时候，在相对于大的作业角度范围处于小的加工角度侧的规定的小的工作角度范围内。

2. 发明申请

US20130133401A1 APPARATUS AND METHOD FOR DETECTING ABNORMALITY OF IMBALANCE OF AIR-FUEL RATIOS AMONG CYLINDERS 有权
标题翻译：检测气缸排气不平衡异常的装置及方法
公开(公告)号：US20130133401A1
公开(公告)日：2013-05-30
申请号：US13687910
申请日：2012-11-28
申请人： Takashi Yui , Kota Hayashi , Tokiji Ito
发明人： Takashi Yui , Kota Hayashi , Tokiji Ito
IPC分类号： G01M15/04
CPC分类号： G01M15/042 , Y02T10/40
摘要： A detecting apparatus that detects an abnormality of imbalance of air-fuel ratios among cylinders of a multi-cylinder internal combustion engine, which is equipped with a variable working angle mechanism of an intake valve, the detecting apparatus includes an abnormality detection portion that detects a parameter regarding rotational fluctuations of each of the cylinders and detects whether or not there is an abnormality of imbalance of air-fuel ratios among the cylinders. The abnormality detection portion refrains from determining that the air-fuel ratios are normal when the working angle at the time of detection of the parameter is within a predetermined large working angle range, and determines that the air-fuel ratios are normal when the working angle at the time of detection of the parameter is within a predetermined small working angle range that is on a small working angle side with respect to the large working angle range.
摘要翻译：一种检测装置，其检测配备有进气门的可变作用角机构的多缸内燃机的气缸之间的空燃比的不平衡的异常的检测装置，所述检测装置包括：异常检测部，其检测参数关于每个气缸的旋转波动，并且检测气缸之间是否存在空燃比不平衡的异常。当检测到参数时的工作角度在预定的大的工作角度范围内时，异常检测部分不能确定空燃比是正常的，并且当工作角度在检测到参数的时候，在相对于大的作业角度范围处于小的加工角度侧的规定的小的工作角度范围内。

3. 发明申请

US20100295186A1 SEMICONDUCTOR MODULE FOR STACKING AND STACKED SEMICONDUCTOR MODULE 有权
标题翻译：用于堆叠和堆叠半导体模块的半导体模块
公开(公告)号：US20100295186A1
公开(公告)日：2010-11-25
申请号：US12783836
申请日：2010-05-20
申请人： Takeshi Kawabata , Takashi YUI
发明人： Takeshi Kawabata , Takashi YUI
IPC分类号： H01L25/065 , H01L23/488 , H01L23/538
CPC分类号： H01L23/49838 , H01L23/49811 , H01L23/49827 , H01L25/105 , H01L2224/05124 , H01L2224/05147 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/16225 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2225/1023 , H01L2225/1058 , H01L2924/01078 , H01L2924/01079 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/00 , H01L2924/00014
摘要： A pad (15) is provided on a surface connecting a first substrate (11) of a lower layer module with an upper layer module, the pad is partially covered by an insulating film (20) to form an opening section (3) exposing the pad (15), a first connection terminal (2) is formed on the lower surface of the first substrate (11) of the lower layer module, the planar shape of the opening section (3) is different from the planar shape of the first connection terminal (2), the outer shape of the opening section (3) is larger than the first connection terminal (2), and in a transmissive inspection from above, the shape of the lower end of a second connection terminal (30) spreading in the opening section (3) is not concealed by the other terminal. This configuration enables easy and reliable determination of whether bonding sections are satisfactory by a non-destructive inspection.
摘要翻译：在连接下层模块的第一基板（11）与上层模块的表面上设置焊盘（15），所述焊盘部分被绝缘膜（20）覆盖以形成露出衬垫（15），在下层模块的第一衬底（11）的下表面上形成第一连接端子（2），开口部分（3）的平面形状不同于第一衬底连接端子（2），开口部（3）的外形大于第一连接端子（2），在从上方透射检查中，第二连接端子（30）的下端的形状扩展在开口部（3）中没有被另一个端子隐藏。该结构能够通过非破坏性检查来容易且可靠地确定接合部分是否令人满意。

4. 发明申请

US20100283129A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100283129A1
公开(公告)日：2010-11-11
申请号：US12773507
申请日：2010-05-04
申请人： Michinari TETANI , Takashi Yui , Minoru Fujisaku
发明人： Michinari TETANI , Takashi Yui , Minoru Fujisaku
IPC分类号： H01L23/544 , H01L21/77
CPC分类号： H01L23/295 , H01L23/3114 , H01L23/562 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2924/01019 , H01L2924/01029 , H01L2924/01078 , H01L2924/12036 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： An upper surface of a semiconductor substrate includes a first portion where a dielectric film is provided, and a second portion where the dielectric film is not provided, wherein the second portion is located in the periphery of the first portion. The upper surface of the semiconductor substrate is covered with a sealing resin.
摘要翻译：半导体衬底的上表面包括设置电介质膜的第一部分和不设置电介质膜的第二部分，其中第二部分位于第一部分的周边。半导体衬底的上表面被密封树脂覆盖。

5. 发明申请

US20070187811A1 Stacked chip semiconductor device and method for manufacturing the same 有权
标题翻译：堆叠式芯片半导体器件及其制造方法
公开(公告)号：US20070187811A1
公开(公告)日：2007-08-16
申请号：US11717953
申请日：2007-03-14
申请人： Yoshiyuki Arai , Takashi Yui , Fumito Itou , Yasutake Yaguchi , Toshitaka Akahoshi
发明人： Yoshiyuki Arai , Takashi Yui , Fumito Itou , Yasutake Yaguchi , Toshitaka Akahoshi
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/3121 , H01L24/73 , H01L2224/05554 , H01L2224/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/49173 , H01L2224/73204 , H01L2224/73265 , H01L2224/92125 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06555 , H01L2225/06582 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip. Thereby, influences of the fillet made of the adhesive are suppressed, allowing miniaturization of the device and improvement in the mass-productivity.
摘要翻译：一种堆叠式芯片半导体器件，包括：具有电极焊盘的衬底; 第一半导体芯片，其经由第一粘合剂层倒装芯片封装在所述基板上; 第二半导体芯片，其安装在所述第一半导体芯片的上部并且具有电极焊盘; 用于电连接第二半导体芯片的电极焊盘和基板的电极焊盘的导线; 以及用于封装第一半导体芯片，第二半导体芯片和电线的模制树脂，第一粘合剂层在第一半导体芯片的周围形成圆角。第一半导体芯片以其中心轴偏离基板的中心轴线的方式设置，偏移被设置成使得第一半导体芯片朝向与圆角的边缘的最大长度相反的一侧偏移第一个半导体芯片。由此，抑制了由粘合剂制成的圆角的影响，从而使装置小型化并提高了批量生产率。

6. 发明授权

US07078818B2 Semiconductor device 有权
公开(公告)号：US07078818B2
公开(公告)日：2006-07-18
申请号：US10766892
申请日：2004-01-30
申请人： Hiroaki Fujimoto , Yoshinobu Kunitomo , Takashi Yui
发明人： Hiroaki Fujimoto , Yoshinobu Kunitomo , Takashi Yui
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/0657 , H01L25/0652 , H01L2224/05554 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.

7. 发明申请

US20060079023A1 Semiconductor device and manufacturing method for the same 审中-公开
公开(公告)号：US20060079023A1
公开(公告)日：2006-04-13
申请号：US11281366
申请日：2005-11-18
申请人： Toshiyuki Fukuda , Hiroaki Fujimoto , Mutsuo Tsuji , Takashi Yui , Yoshiaki Takeoka
发明人： Toshiyuki Fukuda , Hiroaki Fujimoto , Mutsuo Tsuji , Takashi Yui , Yoshiaki Takeoka
IPC分类号： H01L21/60
CPC分类号： H01L21/561 , H01L21/563 , H01L23/3121 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/97 , H01L25/0657 , H01L29/0657 , H01L2224/0401 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48471 , H01L2224/48624 , H01L2224/4943 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/78301 , H01L2224/83191 , H01L2224/83855 , H01L2224/85181 , H01L2224/85186 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06555 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01204 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10162 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/19103 , H01L2924/19105 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/351 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2924/01046 , H01L2924/00012 , H01L2924/00011 , H01L2924/3512 , H01L2224/92247 , H01L2224/4554
摘要： A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip, is significantly larger than the first semiconductor chip in a configuration wherein two semiconductor chips are stacked and mounted on a wiring board. In this semiconductor device the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the side of the adhesive is inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the side of the first semiconductor chip. Therefore, it becomes possible to prevent the occurrence of microcracks in the second semiconductor chip and to prevent the occurrence of defective fine metal wire connections caused by the impact at the time of electrical connection of the second semiconductor chip to the wiring board.

8. 发明授权

US06777796B2 Stacked semiconductor chips on a wiring board 有权
标题翻译：堆叠的半导体芯片在接线板上
公开(公告)号：US06777796B2
公开(公告)日：2004-08-17
申请号：US10320362
申请日：2002-12-17
申请人： Hiroaki Fujimoto , Yoshinobu Kunitomo , Takashi Yui
发明人： Hiroaki Fujimoto , Yoshinobu Kunitomo , Takashi Yui
IPC分类号： H01L2302
CPC分类号： H01L25/0657 , H01L25/0652 , H01L2224/05554 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
摘要翻译：一种半导体器件，包括：布线板; 第一半导体芯片，其具有垂直相对的电路侧和非电路侧，并且经由凸起电极电连接到布线板，第一芯片的电路侧面对布线板的主表面 ; 以及第二半导体芯片，其具有垂直彼此面对并且在其电路侧上包括外部电极的电路侧和非电路侧。第一和第二半导体芯片的非电路侧彼此固定。第二半导体芯片的外部电极通过金属细线连接到布线板。外电极和凸起电极被布置为从布线板的主表面的垂直向下观察不彼此重叠。

9. 发明授权

US06707143B2 Stacked semiconductor chips attached to a wiring board 有权
标题翻译：堆叠的半导体芯片附着在布线板上
公开(公告)号：US06707143B2
公开(公告)日：2004-03-16
申请号：US10320379
申请日：2002-12-17
申请人： Hiroaki Fujimoto , Yoshinobu Kunitomo , Takashi Yui
发明人： Hiroaki Fujimoto , Yoshinobu Kunitomo , Takashi Yui
IPC分类号： H01L2302
CPC分类号： H01L25/0657 , H01L25/0652 , H01L2224/05554 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
摘要翻译：一种半导体器件，包括：布线板; 第一半导体芯片，其具有垂直相对的电路侧和非电路侧，并且经由凸起电极电连接到布线板，第一芯片的电路侧面对布线板的主表面 ; 以及第二半导体芯片，其具有垂直彼此面对并且在其电路侧上包括外部电极的电路侧和非电路侧。第一和第二半导体芯片的非电路侧彼此固定。第二半导体芯片的外部电极通过金属细线连接到布线板。外电极和凸起电极被布置为从布线板的主表面的垂直向下观察不彼此重叠。

10. 发明授权

US07964475B2 Semiconductor wafer, method of manufacturing the same and semiconductor device 有权
标题翻译：半导体晶片及其制造方法以及半导体器件
公开(公告)号：US07964475B2
公开(公告)日：2011-06-21
申请号：US11951441
申请日：2007-12-06
申请人： Yukiko Haraguchi , Takahiro Kumakawa , Takashi Yui , Kazumi Watase
发明人： Yukiko Haraguchi , Takahiro Kumakawa , Takashi Yui , Kazumi Watase
IPC分类号： H01L27/00 , H01L21/82
CPC分类号： H01L21/78
摘要： A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.
摘要翻译：在切割区域3的切割点的外侧形成改质层5和改质层8.因此，在切割点的不同物理性质之间不形成另一界面，可以防止从界面在半导体元件2和半导体基板1之间以及在切割期间从半导体元件的表面，从而抑制了对半导体元件的切屑的发展。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式