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1. 发明申请

US20110260784A1 DECOUPLING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：解耦电路和半导体集成电路
公开(公告)号：US20110260784A1
公开(公告)日：2011-10-27
申请号：US13089253
申请日：2011-04-18
申请人： Masatomo EIMITSU , Takanori SAEKI
发明人： Masatomo EIMITSU , Takanori SAEKI
IPC分类号： G05F3/02
CPC分类号： H03K19/00361 , H03K17/162 , H03K19/00384 , H03K19/0948
摘要： A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.
摘要翻译：去耦电路包括一个反相器。逆变器包括i（i为1以上的整数）各自具有第一栅电极的PMOS晶体管，j（j为0以上的整数）PMOS晶体管。逆变器包括m（m为1以上的整数）各自具有第三栅电极的NMOS晶体管，n（n为0以上的整数）各自具有第四栅电极的NMOS晶体管。第一至第四栅电极耦合到逆变器的输入端。第一和第二栅电极的总面积与第三和第四栅电极的总面积不同。

2. 发明授权

US07912167B2 Clock and data recovery circuit 失效
标题翻译：时钟和数据恢复电路
公开(公告)号：US07912167B2
公开(公告)日：2011-03-22
申请号：US11699007
申请日：2007-01-29
申请人： Takanori Saeki
发明人： Takanori Saeki
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/0814 , H04L7/0025
摘要： A clock and data recovery circuit includes a four-phase generation circuit that generates four-phase clock signals with phases thereof being equally spaced by 90 degrees, a first interpolator and a second interpolator, each of which receives two of the clocks with phases thereof separated to each other by 180 degrees, performs phase interpolation, and outputs a signal obtained by the interpolation and a signal with a phase reverse to a phase of the interpolated signal. A four-phase to eight-phase conversion circuit receives the four-phase clocks from the first and second interpolators, buffers the four-phase clock signals output from the first interpolator and the second interpolator and outputs the buffered four-phase clock signals without alteration, and generates four-phase clocks each obtained by interpolation of two of the clock signals with the mutually adjacent phases among the four-phase clock signals output from the first interpolator and the second interpolator.
摘要翻译：时钟和数据恢复电路包括四相产生电路，其产生其相位等于90度的四相时钟信号，第一内插器和第二内插器，每个内插器和第二内插器接收两个时钟，其相位分离相互相差180度，进行相位插值，并且输出通过内插获得的信号和与内插信号的相位相反的信号。四相到八相转换电路从第一和第二内插器接收四相时钟，缓冲从第一内插器和第二内插器输出的四相时钟信号，并输出缓冲的四相时钟信号而不改变并且产生通过从从第一内插器和第二内插器输出的四相时钟信号中相互相邻的两个时钟信号的内插而获得的四相时钟。

3. 发明授权

US07734001B2 Fractional frequency divider circuit and data transmission apparatus using the same 失效
标题翻译：分数分频器电路和数据传输装置使用相同
公开(公告)号：US07734001B2
公开(公告)日：2010-06-08
申请号：US11052819
申请日：2005-02-09
申请人： Takanori Saeki
发明人： Takanori Saeki
IPC分类号： H03D3/24
CPC分类号： H03K23/546 , H03L7/1974
摘要： A fractional frequency divider circuit with a small circuit scale that outputs a clock with a duty ratio of 50%, and a data transmission apparatus comprising same. The fractional frequency divider circuit is constituted by multiple master-slave flip-flops, and comprises an integer frequency divider circuit that frequency-divides a clock signal with a frequency-division ratio of 1/N(N is an integer), and a logic circuit into which multiple signals outputted from master stages and slave stages of the master-slave flip-flops are inputted and that outputs a signal with a duty ratio of 50% obtained by frequency-dividing the clock signal with a frequency-division ratio of 2/N. The data transmission apparatus is constituted such that it is possible to switch over between a frequency-multiplied clock outputted by a PLL and a clock obtained by frequency-dividing the frequency-multiplied clock with the fractional frequency divider circuit for each channel.
摘要翻译：具有小占空比为50％的时钟的小电路规模的分数分频器电路和包括该时钟的数据发送装置。分数分频器电路由多个主从触发器构成，并且包括对分频比为1 / N（N为整数）的时钟信号进行分频的整数分频器电路和逻辑输入从主从触发器的主级和从级输出的多个信号的电路，并且以分频比2输出通过对时钟信号进行分频而获得的占空比为50％的信号 / N。数据传输装置被构造成使得可以在由PLL输出的倍频时钟和通过用频率分频电路对频率倍频时钟进行分频所获得的时钟之间进行切换。

4. 发明申请

US20090091406A1 COMPACT VIA TRANSMISSION LINE FOR PRINTED CIRCUIT BOARD AND DESIGN METHOD OF THE SAME 有权
标题翻译：通过印刷电路板的传输线及其设计方法来实现
公开(公告)号：US20090091406A1
公开(公告)日：2009-04-09
申请号：US12249273
申请日：2008-10-10
申请人： Taras KUSHTA , Kaoru Narita , Takanori Saeki , Tomoyuki Kaneko , Hirokazu Tohya
发明人： Taras KUSHTA , Kaoru Narita , Takanori Saeki , Tomoyuki Kaneko , Hirokazu Tohya
IPC分类号： H01P1/00
CPC分类号： H05K1/0222 , H01P3/06 , H05K1/024 , H05K1/0251 , H05K3/429 , H05K2201/0187 , H05K2201/09063 , H05K2201/09536 , H05K2201/09618 , H05K2201/09718 , H05K2201/09809
摘要： A compact via transmission line for a printed circuit board having preferred characteristic impedance and capable of miniaturizing the printed circuit board including a multilayer printed circuit board, and extending the frequency range of a via transmission line mounted on the printed circuit board, and a design method of the same. The transmission line has a central conductor forming an inner conductor layer boundary make up a signal via hole, a plurality of via holes arranged around the central conductor form an outer conductor layer boundary, and a plurality of conductor plates formed of a printed circuit board conductor layer, is further provided with a constitutive parameter adjustment clearance hole between the inner and outer conductor layer boundaries of the compact via transmission line, and electrically isolates to prevent cross-talk of a signal propagating through a signal via hole with other signals in a high-frequency signal band.
摘要翻译：一种用于具有优选特性阻抗并能够使包括多层印刷电路板的印刷电路板小型化并且扩展安装在印刷电路板上的通孔传输线的频率范围的印刷电路板的紧凑型通路传输线，以及设计方法一样的。传输线具有形成内导体层边界的中心导体，构成信号通孔，围绕中心导体布置的多个通孔形成外导体层边界，以及由印刷电路板导体形成的多个导体板通过传输线在压缩体的内部和外部导体层边界之间进一步设置本构参数调整间隙孔，并且电隔离以防止通过信号通孔传播的信号与其他信号在高电平中的串扰频率信号频带。

5. 发明申请

US20070205847A1 Via transmission lines for multilayer printed circuit boards 有权
标题翻译：通过多层印刷电路板的传输线
公开(公告)号：US20070205847A1
公开(公告)日：2007-09-06
申请号：US10598134
申请日：2005-03-09
申请人： Taras Kushta , Kaoru Narita , Hirokazu Tohya , Takanori Saeki , Tomoyuki Kaneko
发明人： Taras Kushta , Kaoru Narita , Hirokazu Tohya , Takanori Saeki , Tomoyuki Kaneko
IPC分类号： H01P5/02
CPC分类号： H05K1/0222 , H05K1/0269 , H05K3/429 , H05K2201/09536 , H05K2201/09618 , H05K2201/09718 , H05K2201/09809
摘要： A via transmission line for a multilayer printed circuit board (PCB) in which a wave guiding channel is formed by a signal via or a number of signal vias, an assembly of ground vias surrounding the signal via or corresponding number of coupled signal vias, a set of ground plates from conductor layers of the multilayer PCB, and a clearance hole. In this via transmission line, the signal via, or the number of signal vias forms an inner conductive boundary, ground vias and ground plates from conductor layers of the multilayer PCB form an outer conductive boundary, and the clearance hole provides both isolation of the inner conductive boundary from the outer conductive boundary and high-performance broadband operation of the via transmission line by means of the predetermined clearance hole cross-sectional shape and dimensions where the cross-sectional shape of the clearance hole is defined by the arrangement of ground vias in the outer conductive boundary and dimensions of the clearance hole are determined according to a method to minimize frequency-dependent return losses caused by specific corrugations of the outer conductive boundary formed by ground plates in the wave guiding channel of the via transmission line.
摘要翻译：一种用于多层印刷电路板（PCB）的通孔传输线，其中通过信号通道或多个信号通路形成波导通道，围绕信号通孔或相应数量的耦合信号通孔的接地通孔的组件，多层PCB的导体层的接地板组以及间隙孔。在这个通过传输线路中，信号通孔或信号通道的数量形成内部导电边界，从多层PCB的导体层形成的接地孔和接地板形成外部导电边界，并且间隙孔提供内部通过外部导电边界的导电边界和通孔传输线的高性能宽带操作，借助于预定的间隙孔横截面形状和尺寸，其中间隙孔的横截面形状由接地通孔的布置根据通过在通孔传输线的波导通道中由接地板形成的外导电边界的特定波纹引起的频率相关的返回损耗的方法来确定间隙孔的外导电边界和尺寸。

6. 发明授权

US07187727B2 Clock and data recovery circuit and clock control method 失效
标题翻译：时钟和数据恢复电路和时钟控制方法
公开(公告)号：US07187727B2
公开(公告)日：2007-03-06
申请号：US10022551
申请日：2001-12-17
申请人： Takanori Saeki
发明人： Takanori Saeki
IPC分类号： H03D3/18 , H03D3/24
CPC分类号： H04L7/0337 , H03K5/133 , H03K2005/00065 , H03K2005/00071
摘要： To provide a clock and data recovery circuit which facilitates alteration of the frequency range and adjustment of characteristics. The clock and data recovery circuit includes a phase shift circuit 101 having a switch receiving as inputs multi-phase clocks for selecting and outputting plural sets of the paired clocks from the input multi-phase clocks and a plural number of interpolators receiving the plural number of clock pairs output from the switch to output signals having the delay prescribed by the time corresponding to interior division of the phase difference of the clock pairs, a plural number of latch circuits 102 for latching the input data based on the signals output from the phase shift circuit 101, a counter 103 for counting the outputs of the plural latch circuits, a filter 105 for averaging the counter output over a preset time, a decoder 106 for decoding an output of the filter and a selection circuit 104 fed with a plural number of sets of data output by the plural latch circuits and clocks output from a preset one of the plural interpolators to select pairs of output data and clocks.
摘要翻译：提供便于更改频率范围和调整特性的时钟和数据恢复电路。时钟和数据恢复电路包括：相移电路101，其具有接收作为输入多相时钟的开关的开关，用于从输入的多相时钟选择和输出多组成对的时钟;以及多个内插器，其接收多个从开关输出的时钟对具有由对应于时钟对的相位差的内部分割的时间规定的延迟的输出信号;多个锁存电路102，用于基于从相移输出的信号来锁存输入数据电路101，用于对多个锁存电路的输出进行计数的计数器103，用于在预设时间内对计数器输出进行平均的滤波器105，用于对滤波器的输出进行解码的解码器106和馈送多个由多个锁存电路输出的数据组和从多个内插器中的预置的一个输出的时钟输出，以选择输出数据和时钟对。

7. 发明授权

US07054404B2 Clock control method, frequency dividing circuit and PLL circuit 失效
公开(公告)号：US07054404B2
公开(公告)日：2006-05-30
申请号：US10225361
申请日：2002-08-22
申请人： Takanori Saeki
发明人： Takanori Saeki
IPC分类号： H03D3/24
CPC分类号： H03L7/1976 , G06F7/68 , H03K2005/00065 , H03K2005/00071 , H03L7/081 , H03L7/0891 , H03L7/1974
摘要： A PLL circuit includes a phase comparator; a charge pump; a loop filter; a voltage-controlled oscillator; a frequency dividing circuit; an A counter for dividing the P-frequency-divided output; circuits for generating two signals, which have a phase difference equivalent to one period of the P-frequency-divided output of the frequency dividing circuit; and an interpolator for producing an output signal obtained by interpolating the phase difference between the two signals in accordance with an interior division ratio. The interpolator interpolates in steps of a value obtained by dividing the phase difference by P and incrementing or decrementing a value B, which decides an interior division ratio B:P−B, by B whenever frequency-division by A is performed, and a control circuit. The phase of the output of the interpolator is fed to the phase comparator and compared with the phase of a reference clock, and divides by a frequency-dividing factor.

8. 发明授权

US07042268B2 Clock control circuit and method 失效
公开(公告)号：US07042268B2
公开(公告)日：2006-05-09
申请号：US10844549
申请日：2004-05-13
申请人： Takanori Saeki
发明人： Takanori Saeki
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： H04L7/0008 , G06F1/10 , H03K5/133 , H03K5/14 , H04L7/0337
摘要： A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

9. 发明授权

US06900680B2 Clock controlling method and circuit 有权
公开(公告)号：US06900680B2
公开(公告)日：2005-05-31
申请号：US10851272
申请日：2004-05-21
申请人： Takanori Saeki
发明人： Takanori Saeki
IPC分类号： G06F1/06 , G06F1/08 , H03H17/06 , H03K5/00 , H03K5/131 , H03K5/135 , H03L7/00 , H03L7/08
CPC分类号： H03L7/00 , H03K5/133 , H03K2005/00065 , H03K2005/00071
摘要： A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

10. 发明授权

US06828839B2 Clock period sensing circuit 失效
标题翻译：时钟周期传感电路
公开(公告)号：US06828839B2
公开(公告)日：2004-12-07
申请号：US09511772
申请日：2000-02-24
申请人： Takanori Saeki
发明人： Takanori Saeki
IPC分类号： H03H1126
CPC分类号： H03K5/131 , H03K2005/00071
摘要： Disclosed is a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc., by performing coarse period adjustment in advance. A plurality of delay sensing circuits having slightly overlapping operating ranges and different centers of operation are connected in parallel with respect to a an input clock signal, which is passed through the delay sensing circuits. The period of the clock is sensed coarsely in short periods using a signal which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed.
摘要翻译：公开了一种时钟周期检测电路，其中可以通过预先执行粗略的周期调整来扩大相位调整和倍频器电路等的工作范围。具有稍微重叠的操作范围和不同操作中心的多个延迟感测电路相对于通过延迟感测电路的输入时钟信号并联连接。使用识别时钟信号经过的延迟感测电路的信号和时钟信号未通过的延迟感测电路，在短时间内粗略地感测时钟周期。

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