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1. 发明申请

US20110163789A1 DUTY CYCLE CORRECTION CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE AND SEMICONDUCTOR DEVICE INCLUDING THE DUTY CYCLE CORRECTION CIRCUIT 审中-公开
标题翻译：占空比校正电路和校正占空周期和半导体器件的方法，包括占空比校正电路
公开(公告)号：US20110163789A1
公开(公告)日：2011-07-07
申请号：US12816581
申请日：2010-06-16
申请人： Tae-Sik Na , Seok-Hun Hyun
发明人： Tae-Sik Na , Seok-Hun Hyun
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00058
摘要： Provided are a duty cycle correction circuit and method for correcting a duty cycle, and a semiconductor device including the duty cycle correction circuit. The duty cycle correction circuit includes a code generator configured to generate a first and a second duty code for adjusting the duty cycle of a clock to a target duty cycle, and a duty cycle corrector including a plurality of inverter circuits connected in series and whose driving capabilities are adjusted in response to the first and second duty code, wherein the duty cycle corrector is configured to correct the duty cycle of the clock based on the driving capabilities of the inverter circuits and to output a corrected clock.
摘要翻译：提供了一种用于校正占空比的占空比校正电路和方法，以及包括占空比校正电路的半导体器件。占空比校正电路包括代码发生器，其被配置为产生用于将时钟的占空比调整为目标占空比的第一和第二占空比，以及占空比校正器，其包括串联连接并且驱动的多个反相器电路响应于第一和第二占空比调整功能，其中占空比校正器被配置为基于反相器电路的驱动能力校正时钟的占空比并输出校正的时钟。

2. 发明申请

US20110298513A1 DUTY CORRECTING CIRCUIT, DELAY-LOCKED LOOP CIRCUIT AND METHOD OF CORRECTING DUTY 有权
标题翻译：负载校正电路，延迟锁定环路和校正方法
公开(公告)号：US20110298513A1
公开(公告)日：2011-12-08
申请号：US13078151
申请日：2011-04-01
申请人： Tae-Sik Na , Jun-Bae Kim
发明人： Tae-Sik Na , Jun-Bae Kim
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： The duty correcting circuit includes a duty cycle corrector, a duty detector and a duty correction code generator. The duty cycle corrector corrects a duty cycle of an input clock signal to generate an output clock signal. The duty detector adjusts a delay time of the output clock signal to generate a sampling clock signal, samples the output clock signal in response to the sampling clock signal to generate sample data, and detects a duty of the output clock signal based on logic states of the sample data. Therefore, the duty correcting circuit precisely detects and corrects a duty of the output clock signal.
摘要翻译：占空比校正电路包括占空比校正器，占空比检测器和占空比校正码发生器。占空比校正器校正输入时钟信号的占空比以产生输出时钟信号。占空比检测器调节输出时钟信号的延迟时间以产生采样时钟信号，响应于采样时钟信号采样输出时钟信号以产生采样数据，并且基于逻辑状态检测输出时钟信号的占空比样本数据。因此，占空比校正电路精确地检测并校正输出时钟信号的占空比。

3. 发明授权

US08542045B2 Duty correcting circuit, delay-locked loop circuit and method of correcting duty 有权
标题翻译：负责校正电路，延迟锁定环路电路及其校正方法
公开(公告)号：US08542045B2
公开(公告)日：2013-09-24
申请号：US13078151
申请日：2011-04-01
申请人： Tae-Sik Na , Jun-Bae Kim
发明人： Tae-Sik Na , Jun-Bae Kim
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03K5/1565
摘要： The duty correcting circuit includes a duty cycle corrector, a duty detector and a duty correction code generator. The duty cycle corrector corrects a duty cycle of an input clock signal to generate an output clock signal. The duty detector adjusts a delay time of the output clock signal to generate a sampling clock signal, samples the output clock signal in response to the sampling clock signal to generate sample data, and detects a duty of the output clock signal based on logic states of the sample data. Therefore, the duty correcting circuit precisely detects and corrects a duty of the output clock signal.
摘要翻译：占空比校正电路包括占空比校正器，占空比检测器和占空比校正码发生器。占空比校正器校正输入时钟信号的占空比以产生输出时钟信号。占空比检测器调节输出时钟信号的延迟时间以产生采样时钟信号，响应于采样时钟信号采样输出时钟信号以产生采样数据，并且基于逻辑状态检测输出时钟信号的占空比样本数据。因此，占空比校正电路精确地检测并校正输出时钟信号的占空比。

4. 发明授权

US08373475B2 Phase interpolator and delay locked-loop circuit 有权
标题翻译：相位内插器和延迟锁相环电路
公开(公告)号：US08373475B2
公开(公告)日：2013-02-12
申请号：US13270509
申请日：2011-10-11
申请人： Tae-Sik Na , Yang-Ki Kim
发明人： Tae-Sik Na , Yang-Ki Kim
IPC分类号： H03L7/06
CPC分类号： H03H11/16 , H03L7/0818
摘要： A phase interpolator includes a delay difference detector and a phase interpolation driver. The delay difference detector receives a delay code to detect a delay difference. The phase interpolation driver includes two or more driver blocks complementarily operating, and the phase interpolation driver interpolate two input signals in response to the delay difference to provide an interpolated output signal. Each of two or more driver blocks includes a plurality of unit drivers, each input of the unit drivers is commonly connected, and each delay of the two or more driver blocks is varied according to the delay difference.
摘要翻译：相位插值器包括延迟差检测器和相位插值驱动器。延迟差检测器接收延迟码以检测延迟差。相位插值驱动器包括两个或更多个驱动器块互补操作，并且相位插值驱动器响应于延迟差内插两个输入信号以提供内插输出信号。两个或更多个驱动器块中的每一个包括多个单元驱动器，单元驱动器的每个输入共同连接，并且两个或更多个驱动器块的每个延迟根据延迟差异而变化。

5. 发明申请

US20120086486A1 PHASE INTERPOLATOR AND DELAY LOCKED-LOOP CIRCUIT 有权
标题翻译：相位插补器和延迟锁定环路
公开(公告)号：US20120086486A1
公开(公告)日：2012-04-12
申请号：US13270509
申请日：2011-10-11
申请人： Tae-Sik NA , Yang-Ki Kim
发明人： Tae-Sik NA , Yang-Ki Kim
IPC分类号： H03L7/08 , H03H11/16
CPC分类号： H03H11/16 , H03L7/0818
摘要： A phase interpolator includes a delay difference detector and a phase interpolation driver. The delay difference detector receives a delay code to detect a delay difference. The phase interpolation driver includes two or more driver blocks complementarily operating, and the phase interpolation driver interpolate two input signals in response to the delay difference to provide an interpolated output signal. Each of two or more driver blocks includes a plurality of unit drivers, each input of the unit drivers is commonly connected, and each delay of the two or more driver blocks is varied according to the delay difference.
摘要翻译：相位插值器包括延迟差检测器和相位插值驱动器。延迟差检测器接收延迟码以检测延迟差。相位插值驱动器包括两个或更多个驱动器块互补操作，并且相位插值驱动器响应于延迟差内插两个输入信号以提供内插输出信号。两个或更多个驱动器块中的每一个包括多个单元驱动器，单元驱动器的每个输入共同连接，并且两个或更多个驱动器块的每个延迟根据延迟差异而变化。

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