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1. 发明授权

US08779429B2 Display substrate and method of manufacturing the same 有权
标题翻译：显示基板及其制造方法
公开(公告)号：US08779429B2
公开(公告)日：2014-07-15
申请号：US13565639
申请日：2012-08-02
申请人： O-Sung Seo , Hwa-Yeul Oh , Hyoung-Cheol Lee , Tae-Kyung Yim
发明人： O-Sung Seo , Hwa-Yeul Oh , Hyoung-Cheol Lee , Tae-Kyung Yim
IPC分类号： H01L27/14 , H01L21/84
CPC分类号： H01L27/124 , H01L27/3272 , H01L27/3279 , H01L29/78633
摘要： RC delay in gate lines of a wide display is reduced by using a low resistivity conductor in the gate lines and a different conductor for forming corresponding gate electrodes. More specifically, a corresponding display substrate includes a gate line made of a first gate line metal, a data line made of a first data line metal, a pixel transistor and a first connection providing part. The pixel transistor includes a first active pattern formed of polycrystalline silicon (poly-Si) and a first gate electrode formed there above and made of a conductive material different from the first gate line metal. The first connection providing part connects the first gate electrode to the gate line. On the other hand, the source electrode is integrally extended from the data line.
摘要翻译：通过在栅极线中使用低电阻率导体和用于形成对应的栅电极的不同导体来减小宽显示器的栅极线中的RC延迟。更具体地，对应的显示基板包括由第一栅极线金属制成的栅极线，由第一数据线金属制成的数据线，像素晶体管和第一连接提供部。像素晶体管包括由多晶硅（poly-Si）形成的第一有源图案和形成在其上方并由不同于第一栅极线金属的导电材料制成的第一栅电极。第一连接提供部分将第一栅电极连接到栅极线。另一方面，源电极从数据线整体延伸。

2. 发明申请

US20130037813A1 CRYSTALLIZATION METHOD OF THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD FOR THIN FILM TRANSISTOR ARRAY PANEL 有权
标题翻译：薄膜晶体管，薄膜晶体管阵列的结晶方法和薄膜晶体管阵列的制造方法
公开(公告)号：US20130037813A1
公开(公告)日：2013-02-14
申请号：US13535007
申请日：2012-06-27
申请人： Joo-Han Kim , Hwa-Dong Jung , Wan-Soon Lim , Jee-Hun Lim , Joo Seok Yeom , Tae-Kyung Yim , Jae-Hak Lee , Hyuk Soon Kwon , Hyoung Cheol Lee , Jeong-Ju Park , Se-Myung Kwon , So-Young Koo
发明人： Joo-Han Kim , Hwa-Dong Jung , Wan-Soon Lim , Jee-Hun Lim , Joo Seok Yeom , Tae-Kyung Yim , Jae-Hak Lee , Hyuk Soon Kwon , Hyoung Cheol Lee , Jeong-Ju Park , Se-Myung Kwon , So-Young Koo
IPC分类号： H01L33/08
CPC分类号： H01L29/78663 , H01L27/1222 , H01L27/1285
摘要： Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.
摘要翻译：本发明的示例性实施例公开了一种制造薄膜晶体管阵列面板的方法，其具有缩短的总体处理时间并提供均匀的结晶。本发明的示例性实施例还公开了一种薄膜晶体管的结晶方法，包括在基板上形成包括第一像素区域，第二像素区域和第三像素区域的半导体层。结晶方法包括使用微透镜阵列结晶对应于薄膜晶体管的沟道区的半导体层的一部分。

3. 发明授权

US08741672B2 Crystallization method of thin film transistor, thin film transistor array panel and manufacturing method for thin film transistor array panel 有权
标题翻译：薄膜晶体管，薄膜晶体管阵列面板的结晶方法及薄膜晶体管阵列面板的制造方法
公开(公告)号：US08741672B2
公开(公告)日：2014-06-03
申请号：US13535007
申请日：2012-06-27
申请人： Joo-Han Kim , Hwa-Dong Jung , Wan-Soon Lim , Jee-Hun Lim , Joo Seok Yeom , Tae-Kyung Yim , Jae-Hak Lee , Hyuk Soon Kwon , Hyoung Cheol Lee , Jeong-Ju Park , Se-Myung Kwon , So-Young Koo
发明人： Joo-Han Kim , Hwa-Dong Jung , Wan-Soon Lim , Jee-Hun Lim , Joo Seok Yeom , Tae-Kyung Yim , Jae-Hak Lee , Hyuk Soon Kwon , Hyoung Cheol Lee , Jeong-Ju Park , Se-Myung Kwon , So-Young Koo
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/78663 , H01L27/1222 , H01L27/1285
摘要： Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.
摘要翻译：本发明的示例性实施例公开了一种制造薄膜晶体管阵列面板的方法，其具有缩短的总体处理时间并提供均匀的结晶。本发明的示例性实施例还公开了一种薄膜晶体管的结晶方法，包括在基板上形成包括第一像素区域，第二像素区域和第三像素区域的半导体层。结晶方法包括使用微透镜阵列结晶对应于薄膜晶体管的沟道区的半导体层的一部分。

4. 发明申请

US20130234144A1 DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：显示基板及其制造方法
公开(公告)号：US20130234144A1
公开(公告)日：2013-09-12
申请号：US13565639
申请日：2012-08-02
申请人： O-Sung SEO , Hwa-Yeul OH , Hyoung-Cheol LEE , Tae-Kyung YIM
发明人： O-Sung SEO , Hwa-Yeul OH , Hyoung-Cheol LEE , Tae-Kyung YIM
IPC分类号： H01L27/15 , H01L33/08
CPC分类号： H01L27/124 , H01L27/3272 , H01L27/3279 , H01L29/78633
摘要： RC delay in gate lines of a wide display is reduced by using a low resistivity conductor in the gate lines and a different conductor for forming corresponding gate electrodes. More specifically, a corresponding display substrate includes a gate line made of a first gate line metal, a data line made of a first data line metal, a pixel transistor and a first connection providing part. The pixel transistor includes a first active pattern formed of polycrystalline silicon (poly-Si) and a first gate electrode formed there above and made of a conductive material different from the first gate line metal. The first connection providing part connects the first gate electrode to the gate line. On the other hand, the source electrode is integrally extended from the data line.
摘要翻译：通过在栅极线中使用低电阻率导体和用于形成对应的栅电极的不同导体来减小宽显示器的栅极线中的RC延迟。更具体地，对应的显示基板包括由第一栅极线金属制成的栅极线，由第一数据线金属制成的数据线，像素晶体管和第一连接提供部。像素晶体管包括由多晶硅（poly-Si）形成的第一有源图案和形成在其上方并由不同于第一栅极线金属的导电材料制成的第一栅电极。第一连接提供部分将第一栅电极连接到栅极线。另一方面，源电极从数据线整体延伸。

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