专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5293512A Semiconductor device having a groove type isolation region 失效
标题翻译：具有凹槽型隔离区域的半导体器件
公开(公告)号：US5293512A
公开(公告)日：1994-03-08
申请号：US834829
申请日：1992-02-13
申请人： Tadashi Nishigoori , Takaaki Kuwata
发明人： Tadashi Nishigoori , Takaaki Kuwata
IPC分类号： H01L21/336 , H01L21/74 , H01L29/06 , H01L29/417 , H01L29/78 , H01L27/02
CPC分类号： H01L23/485 , H01L21/743 , H01L29/0653 , H01L29/41766 , H01L29/66636 , H01L29/7834 , H01L2924/0002
摘要： A semiconductor device is disclosed in which a groove type element isolation region in the surroundings of a first diffused layer of one conductivity type formed on the surface of a silicon substrate of the opposite conductivity type, an insulating film is embedded in the groove type element isolation region, and an interlayer insulating film is provided on the silicon substrate. A contact hole for connecting the first diffused layer to a metallic wiring is provided at a position that straddles the boundary between the first diffused layer and the groove type element isolation region, the insulating film embedded in the groove type element isolation region is exposed in a part of the bottom face of the contact hole, and the silicon substrate including the first diffused layer is exposed on the side face of the contact hole. On the surface of the silicon substrate exposed to the contact hole there is formed a second diffused layer of the one conductivity type, and this diffused layer is connected to the first diffused layer. Because of the structure as described in the above, the increase in the contact resistance between the first and the second diffused layer, and the metallic wiring can be suppressed even if the aperture of the contact hole is decreased. Moreover, it becomes unnecessary to provide a space between the contact hole and the groove type element isolation region so that it becomes possible to reduce the area of the first diffused layer, and it is effective to enhance the operating speed due to the increase in the integration of the semiconductor device and to the decrease in the junction capacitance.
摘要翻译：公开了一种半导体器件，其中形成在相反导电类型的硅衬底的表面上的一种导电类型的第一扩散层的周围的沟槽型元件隔离区域，绝缘膜嵌入在沟槽型元件隔离中区域，并且在硅衬底上设置层间绝缘膜。在跨越第一扩散层和槽型元件隔离区域之间的边界的位置处设置用于将第一扩散层连接到金属布线的接触孔，将嵌入在槽型元件隔离区域中的绝缘膜暴露在接触孔的底面的一部分，包含第一扩散层的硅基板在接触孔的侧面露出。在暴露于接触孔的硅衬底的表面上形成有一种导电类型的第二扩散层，并且该扩散层连接到第一扩散层。由于如上所述的结构，即使接触孔的孔径减小，也可以抑制第一和第二扩散层与金属布线之间的接触电阻的增加。此外，不需要在接触孔和槽型元件隔离区域之间设置空间，从而可以减小第一扩散层的面积，并且由于增加了第一扩散层的面积而提高操作速度是有效的半导体器件的集成和结电容的减小。

2. 发明授权

US5376816A Bi-cmos integrated circuit device having buried region use in common for bipolar and mos transistors 失效
标题翻译： Bi-cmos集成电路器件，其掩埋区域用于双极和mos晶体管
公开(公告)号：US5376816A
公开(公告)日：1994-12-27
申请号：US81799
申请日：1993-06-23
申请人： Tadashi Nishigoori , Kiyotaka Imai
发明人： Tadashi Nishigoori , Kiyotaka Imai
IPC分类号： H01L27/06 , H01L27/02 , H01L27/04 , H01L27/12
CPC分类号： H01L27/0623
摘要： Disclosed herein is a Bi-CMOS IC which includes a semiconductor substrate of one conductivity type, a semiconductor layer of an opposite conductivity type formed on the substrate, a buried region of the opposite conductivity type formed between a first part of the semiconductor layer and the substrate and elongated under a second part of the semiconductor layer to form an elongated buried portion, a bipolar transistor formed in the first part by using the first part as a collector region thereof, a semiconductor region of the one conductivity type formed in the second part in contact with the elongated buried portion separately from the substrate, and an insulated gate transistor formed in the semiconductor region.
摘要翻译：本发明公开了一种Bi-CMOS IC，其包括一种导电类型的半导体衬底，形成在衬底上的相反导电类型的半导体层，形成在半导体层的第一部分和衬底并在半导体层的第二部分下延伸以形成细长的掩埋部分，通过使用第一部分作为其集电极区域形成在第一部分中的双极晶体管，形成在第二部分中的一种导电类型的半导体区域与所述衬底分开地与所述细长掩埋部分接触，以及形成在所述半导体区域中的绝缘栅极晶体管。

3. 发明授权

US5293503A Semiconductor device having multilayer metal interconnection 失效
标题翻译：具有多层金属互连的半导体器件
公开(公告)号：US5293503A
公开(公告)日：1994-03-08
申请号：US943228
申请日：1992-09-10
申请人： Tadashi Nishigoori
发明人： Tadashi Nishigoori
IPC分类号： H01L21/3205 , H01L21/316 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/528 , H05K1/00
CPC分类号： H01L23/5283 , H01L2924/0002
摘要： In a semiconductor device in which the surface of a semiconductor substrate which was subjected to impurity diffusion process, and includes a multilayer metal interconnection layer which is formed on top of it by alternately laminating a metal wiring layer and an interlayer insulating film, the present semiconductor device is characterized in that in a lower layer metal wiring layer there is provided a dummy wiring stripe which is arranged in parallel to two wiring stripes that are formed away from other wiring stripes at a space according to design rules. The width of the wiring stripe is augmented effectively due to the presence of the dummy stripe, and the holding quantity of the material of the coating film which constitutes a part of the interlayer insulating film is increased. Therefore, the flatness of the interlayer insulating film directly over these wiring stripes can be improved, and it becomes possible to secure the uniformity of the film of the upper layer metal wiring layer that is formed on top of the interlayer insulating film.
摘要翻译：在其中进行杂质扩散处理的半导体衬底的表面并且包括通过交替层叠金属布线层和层间绝缘膜而形成在其顶部的多层金属互连层的半导体器件中，本半导体器件的特征在于，在下层金属布线层中设置有虚设布线条，其平行布置成根据设计规则在空间处远离其它布线条形成的布线条。由于存在虚拟条纹，布线条的宽度有效地增加，并且构成层间绝缘膜的一部分的涂膜的材料的保持量增加。因此，可以提高直接在这些布线条上的层间绝缘膜的平坦度，并且可以确保形成在层间绝缘膜的顶部上的上层金属布线层的膜的均匀性。

4. 发明授权

US5245210A MOS type semiconductor device 失效
标题翻译： MOS型半导体器件
公开(公告)号：US5245210A
公开(公告)日：1993-09-14
申请号：US742918
申请日：1991-08-09
申请人： Tadashi Nishigoori
发明人： Tadashi Nishigoori
IPC分类号： H01L21/768 , H01L21/28 , H01L21/336 , H01L23/522 , H01L29/43 , H01L29/78
CPC分类号： H01L23/522 , H01L23/5226 , H01L2924/0002
摘要： In a MOS type semiconductor device, a first contact hole having a length similar to a width of source/drain diffusion layers is opened in a first layer insulation film. In the first contact hole, a refractory metal or the like is filled and a second layer insulation film is formed to cover the same. In the second layer insulation film, a second contact hole having an area smaller than that of the first contact hole is opened and, through this second contact hole, an aluminum interconnection and the source/drain regions are electrically connected. Therefore, it becomes possible to avoid decrease of ON current of a transistor owing to resistance elements of the source/drain diffusion layers and at the same time to reduce an area occupied by the aluminum interconnection to be connected to the source/drain regions on a transistor device.
摘要翻译：在MOS型半导体器件中，在第一层绝缘膜中开放具有与源极/漏极扩散层的宽度相似的长度的第一接触孔。在第一接触孔中，填充难熔金属等，并且形成第二层绝缘膜以覆盖其。在第二层绝缘膜中，打开面积小于第一接触孔的第二接触孔，并且通过该第二接触孔，铝互连并且源/漏区电连接。因此，可以避免由于源/漏扩散层的电阻元件导致的晶体管的导通电流的降低，并且同时减少要连接到源极/漏极区域的铝互连所占据的面积晶体管器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式