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1. 发明授权

US08891213B2 Integrated electrostatic discharge (ESD) device 有权
标题翻译：集成静电放电（ESD）器件
公开(公告)号：US08891213B2
公开(公告)日：2014-11-18
申请号：US13244292
申请日：2011-09-24
申请人： Chi Kang Liu , Ta Lee Yu , Quan Li
发明人： Chi Kang Liu , Ta Lee Yu , Quan Li
IPC分类号： H02H9/00 , H01L27/02 , H01L29/78 , H02H3/22 , H02H3/02 , H02H3/08
CPC分类号： H01L27/0259 , H01L29/7835
摘要： A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.
摘要翻译：用于ESD保护的半导体器件包括形成在衬底内的第一导电类型的半导体衬底和第二导电类型的阱区。井区的特征在于第一深度。该器件包括MOS晶体管，第一双极晶体管和第二双极晶体管。 MOS晶体管包括在阱区内的第二深度的第一轻掺杂漏极（LDD）区域，以及在第一LDD区域内的漏极区域和发射极区域。发射极区域的特征在于第二导电类型。第一双极晶体管与发射极区域，第一LDD区域和阱区域相关联，并且其特征在于第一触发电压。第二双极晶体管与第一LDD区，阱区和衬底相关联，并且其特征在于第二触发电压。

2. 发明申请

US20120014021A1 INTEGRATED ELECTROSTATIC DISCHARGE (ESD) DEVICE 有权
标题翻译：集成静电放电（ESD）器件
公开(公告)号：US20120014021A1
公开(公告)日：2012-01-19
申请号：US13244292
申请日：2011-09-24
申请人： Chi Kang Liu , TA Lee Yu , Quan Li
发明人： Chi Kang Liu , TA Lee Yu , Quan Li
IPC分类号： H02H9/04 , H01L21/332
CPC分类号： H01L27/0259 , H01L29/7835
摘要： A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.
摘要翻译：用于ESD保护的半导体器件包括形成在衬底内的第一导电类型的半导体衬底和第二导电类型的阱区。井区的特征在于第一深度。该器件包括MOS晶体管，第一双极晶体管和第二双极晶体管。 MOS晶体管包括在阱区内的第二深度的第一轻掺杂漏极（LDD）区域，以及在第一LDD区域内的漏极区域和发射极区域。发射极区域的特征在于第二导电类型。第一双极晶体管与发射极区域，第一LDD区域和阱区域相关联，并且其特征在于第一触发电压。第二双极晶体管与第一LDD区，阱区和衬底相关联，并且其特征在于第二触发电压。

3. 发明授权

US08044687B2 Wide input common mode voltage comparator 有权
标题翻译：宽输入共模电压比较器
公开(公告)号：US08044687B2
公开(公告)日：2011-10-25
申请号：US11548696
申请日：2006-10-11
申请人： Ta Lee Yu , Qian Yu Yu
发明人： Ta Lee Yu , Qian Yu Yu
IPC分类号： H03K5/22
CPC分类号： H03K19/018528 , H03K5/003 , H03K5/2472
摘要： A design for a wide input common mode voltage comparator is provided which reduces the delay between outputs from component comparators. The wide input common mode voltage comparator includes a first comparator configured to receive a differential input. The first comparator is further configured to accommodate high common mode voltages. The wide input common mode voltage comparator further includes a second comparator configured to receive the differential input. The first comparator is further configured to accommodate low common mode voltages. Additionally, the threshold voltages of the active devices within the comparator are between −100 to 100 mV. Furthermore, the wide input common mode voltage comparator includes a summing circuit configured to receive the outputs of the first and second comparators to create a single-ended output.
摘要翻译：提供了一种用于宽输入共模电压比较器的设计，其减少了来自元件比较器的输出之间的延迟。宽输入共模电压比较器包括配置为接收差分输入的第一比较器。第一比较器还被配置为适应高共模电压。宽输入共模电压比较器还包括被配置为接收差分输入的第二比较器。第一比较器还被配置为适应低共模电压。此外，比较器内有源器件的阈值电压在-100至100 mV之间。此外，宽输入共模电压比较器包括被配置为接收第一和第二比较器的输出以产生单端输出的求和电路。

4. 发明申请

US20080270662A1 SYSTEM AND METHOD FOR PROVIDING LIVE INSERTION 有权
标题翻译：用于提供活动插入的系统和方法
公开(公告)号：US20080270662A1
公开(公告)日：2008-10-30
申请号：US11780419
申请日：2007-07-19
申请人： Ta Lee Yu , Hai Feng Xue , Hui Juan Cheng
发明人： Ta Lee Yu , Hai Feng Xue , Hui Juan Cheng
IPC分类号： G06F13/00
CPC分类号： G06F13/4081
摘要： System and method for providing live insertion. According to an embodiment, the present invention provides an integrated circuit. The integrated circuit includes a first port configured to be electrically coupled to a pad. The first port includes a first connection, a second connection, and a third connection. The integrated circuit also includes a first resistor having a first terminal and a second terminal. Additionally, the integrated circuit includes a second resistor having a third terminal and a forth terminal. The integrated circuit additionally includes a voltage source configured to provided a first voltage. The integrated circuit further includes a first PMOS transistor having a first gate terminal, a first drain terminal and a first source terminal. In addition, the integrated circuit includes a second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal.
摘要翻译：提供实时插入的系统和方法。根据实施例，本发明提供一种集成电路。集成电路包括被配置为电耦合到焊盘的第一端口。第一端口包括第一连接，第二连接和第三连接。集成电路还包括具有第一端子和第二端子的第一电阻器。此外，集成电路包括具有第三端子和第四端子的第二电阻器。集成电路还包括被配置为提供第一电压的电压源。集成电路还包括具有第一栅极端子，第一漏极端子和第一源极端子的第一PMOS晶体管。此外，集成电路包括具有第二栅极端子，第二漏极端子和第二源极端子的第二PMOS晶体管。

5. 发明授权

US06987303B2 Silicon-controlled rectifier structures on silicon-on insulator with shallow trench isolation 有权
公开(公告)号：US06987303B2
公开(公告)日：2006-01-17
申请号：US10639884
申请日：2003-08-13
申请人： Ta Lee Yu
发明人： Ta Lee Yu
IPC分类号： H01L29/788
CPC分类号： H01L27/0262 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A method to form a SCR device in the manufacture of an integrated circuit device is achieved. The method comprises providing a SOI substrate comprising a silicon layer overlying a buried oxide layer. The silicon layer further comprises a first well of a first type and a second well of a second type. A first heavily doped region of the first type is formed in the second well to form an anode terminal. A second heavily doped region of the second type is formed in the first well to form a cathode terminal and to complete the SCR device. A gate isolation method is described. A salicide method is described. LVT-SCR methods, including a floating-well, LVT-SCR method, are described.

6. 发明授权

US06891230B2 Bipolar ESD protection structure 失效
公开(公告)号：US06891230B2
公开(公告)日：2005-05-10
申请号：US10790925
申请日：2004-03-02
申请人： Ta-Lee Yu
发明人： Ta-Lee Yu
IPC分类号： H01L21/331 , H01L23/62 , H01L27/02 , H01L27/082 , H01L27/102 , H01L29/70 , H01L29/732 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/11 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7322 , H01L27/0259
摘要： The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements. The emitter is contained within the footprint of the collector elements, and enables containment of device size, therefore minimizing device capacitance characteristics important in high speed circuit design. Other embodiments of the invention use variations in the structure of the common contiguous emitter conductor as well as different base conductor structure layouts.

7. 发明授权

US06867103B1 Method of fabricating an ESD device on SOI 有权
标题翻译：在SOI上制造ESD器件的方法
公开(公告)号：US06867103B1
公开(公告)日：2005-03-15
申请号：US10154740
申请日：2002-05-24
申请人： Ta-Lee Yu
发明人： Ta-Lee Yu
IPC分类号： H01L21/336 , H01L27/02 , H01L29/786
CPC分类号： H01L29/66772 , H01L27/0251 , H01L29/78612 , H01L29/78621
摘要： A method to form transistors having improved ESD performance in the manufacture of an integrated circuit device is achieved. The method includes providing a SOI substrate with a doped silicon layer and a buried oxide layer. The doped silicon layer has a first conductivity type and overlies the buried oxide layer. Ions are implanted into the SOI substrate to form higher concentration regions in the doped silicon layer. The higher concentration regions have the first conductivity type and are formed substantially below the top surface of the doped silicon layer. MOS gates are formed. These MOS gates include an electrode layer overlying the doped silicon layer with a gate oxide layer therebetween. Source and drain regions are formed in the doped silicon layer to complete the transistors in the manufacture of the integrated circuit device. The source and drain regions contact the higher concentration regions and have a second conductivity type.
摘要翻译：实现了在集成电路器件的制造中形成具有改进的ESD性能的晶体管的方法。该方法包括提供具有掺杂硅层和掩埋氧化物层的SOI衬底。掺杂硅层具有第一导电类型并且覆盖在掩埋氧化物层上。将离子注入到SOI衬底中以在掺杂硅层中形成更高的浓度区域。较高浓度区域具有第一导电类型并且基本上在掺杂硅层的顶表面下方形成。 MOS门形成。这些MOS栅极包括覆盖掺杂硅层的电极层，其间具有栅氧化层。源极和漏极区域形成在掺杂硅层中以在集成电路器件的制造中完成晶体管。源区和漏区接触较高浓度区并具有第二导电类型。

8. 发明授权

US06815821B2 Method of fabricating seal-ring structure with ESD protection 有权
标题翻译：用ESD保护制造密封环结构的方法
公开(公告)号：US06815821B2
公开(公告)日：2004-11-09
申请号：US10217650
申请日：2002-08-14
申请人： Ta-Lee Yu
发明人： Ta-Lee Yu
IPC分类号： H01L23485
CPC分类号： H01L27/0251 , H01L2224/05
摘要： A seal ring structure having an electrostatic discharge protection function, suitable for a conductive first-type substrate which has a bias provided by a second power source. The new seal ring scheme including a conductive second-type doped diffusion region located on the first-type substrate; and a metal conductive structure, comprising at least a metal layer and a connection conductor, wherein the connection conductor is connected to the conductive second-type doped diffusion region and to a bias provided by a first power source and to the metal layer.
摘要翻译：一种具有静电放电保护功能的密封环结构，适用于具有由第二电源提供的偏压的导电第一型衬底。新的密封环方案包括位于第一型衬底上的导电第二类掺杂扩散区; 以及金属导电结构，其至少包括金属层和连接导体，其中所述连接导体连接到所述导电第二类型掺杂扩散区域并且连接到由第一电源提供的偏压和所述金属层。

9. 发明授权

US06756642B2 Integrated circuit having improved ESD protection 有权
标题翻译：集成电路具有改进的ESD保护
公开(公告)号：US06756642B2
公开(公告)日：2004-06-29
申请号：US10291053
申请日：2002-11-07
申请人： Jian-Hsing Lee , Ta-Lee Yu , Shui-Hung Chen
发明人： Jian-Hsing Lee , Ta-Lee Yu , Shui-Hung Chen
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L29/87
摘要： In a high voltage n-channel MOS structure, inserting p+ diffusion and an n-well into NMOS drain area, along with providing ESD protection by means of forming parasitic SCR, allows using signal of 5V and decreases snapback voltage below 2V.
摘要翻译：在高电压n沟道MOS结构中，将p +扩散和n阱插入NMOS漏极区域，并通过形成寄生SCR提供ESD保护，允许使用5V信号，并将回跳电压降低到2V以下。

10. 发明授权

US06720625B2 Bipolar ESD protection structure 有权
公开(公告)号：US06720625B2
公开(公告)日：2004-04-13
申请号：US10266665
申请日：2002-10-08
申请人： Ta-Lee Yu
发明人： Ta-Lee Yu
IPC分类号： H01L2362
CPC分类号： H01L29/7322 , H01L27/0259
摘要： The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements. The emitter is contained within the footprint of the collector elements, and enables containment of device size, therefore minimizing device capacitance characteristics important in high speed circuit design. Other embodiments of the invention use variations in the structure of the common contiguous emitter conductor as well as different base conductor structure layouts.

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