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1. 发明授权

US09418727B2 Five transistor SRAM cell 有权
标题翻译：五晶体管SRAM单元
公开(公告)号：US09418727B2
公开(公告)日：2016-08-16
申请号：US13561469
申请日：2012-07-30
申请人： Sushil Sudam Sakhare
发明人： Sushil Sudam Sakhare
IPC分类号： G11C11/00 , G11C11/412 , G11C11/419
CPC分类号： G11C11/412 , G11C11/4125 , G11C11/419
摘要： A five transistor static random-access-memory (SRAM) cell is disclosed which can be made part of an SRAM array to provide an improved reduction in size. The cell includes two cross-coupled inverters, each having two complementary transistors, and an n-channel transistor switch connected to a bit line (BL) and a word line (WL). The p-channel element of one of the inverters is connected to a power supply, and the p-channel transistor of the other inverter is coupled to a write bit line (WBL). By varying the voltage levels on the BL and WBL lines the biasing of the individual n-channel transistors of each of the inverters can be changed based on the data to be written to the cell. Various biasing systems are presented such that the SRAM cell memory state can be changed without requiring larger transistor elements to overpower the cell state.
摘要翻译：公开了一种五晶体管静态随机存取存储器（SRAM）单元，其可以被制成SRAM阵列的一部分以提供改进的尺寸减小。该单元包括两个交叉耦合的反相器，每个具有两个互补晶体管，以及连接到位线（BL）和字线（WL）的n沟道晶体管开关。反相器中的一个的p沟道元件连接到电源，另一个反相器的p沟道晶体管耦合到写位线（WBL）。通过改变BL和WBL线上的电压电平，可以基于要写入单元的数据改变每个反相器的各个n沟道晶体管的偏置。呈现各种偏置系统，使得可以改变SRAM单元存储器状态，而不需要较大的晶体管元件来超载电池状态。

2. 发明申请

US20140029333A1 FIVE TRANSISTOR SRAM CELL 有权
标题翻译：五个晶体管SRAM单元
公开(公告)号：US20140029333A1
公开(公告)日：2014-01-30
申请号：US13561469
申请日：2012-07-30
申请人： Sushil Sudam SAKHARE
发明人： Sushil Sudam SAKHARE
IPC分类号： G11C11/412
CPC分类号： G11C11/412 , G11C11/4125 , G11C11/419
摘要： A five transistor static random-access-memory (SRAM) cell is disclosed which can be made part of an SRAM array to provide an improved reduction in size. The cell includes two cross-coupled inverters, each having two complementary transistors, and an n-channel transistor switch connected to a bit line (BL) and a word line (WL). The p-channel element of one of the inverters is connected to a power supply, and the p-channel transistor of the other inverter is coupled to a write bit line (WBL). By varying the voltage levels on the BL and WBL lines the biasing of the individual n-channel transistors of each of the inverters can be changed based on the data to be written to the cell. Various biasing systems are presented such that the SRAM cell memory state can be changed without requiring larger transistor elements to overpower the cell state.
摘要翻译：公开了一种五晶体管静态随机存取存储器（SRAM）单元，其可以被制成SRAM阵列的一部分以提供改进的尺寸减小。该单元包括两个交叉耦合的反相器，每个具有两个互补晶体管，以及连接到位线（BL）和字线（WL）的n沟道晶体管开关。反相器中的一个的p沟道元件连接到电源，另一个反相器的p沟道晶体管耦合到写位线（WBL）。通过改变BL和WBL线上的电压电平，可以基于要写入单元的数据改变每个反相器的各个n沟道晶体管的偏置。呈现各种偏置系统，使得可以改变SRAM单元存储器状态，而不需要较大的晶体管元件来超载电池状态。

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