会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • METHOD AND APPARATUS FOR TESTING A FULLY BUFFERED MEMORY MODULE
    • 用于测试完全缓冲存储器模块的方法和装置
    • US20070140025A1
    • 2007-06-21
    • US11611390
    • 2006-12-15
    • Hong ChanAllen LawrenceSunny ChangJoseph KleinBosco Lai
    • Hong ChanAllen LawrenceSunny ChangJoseph KleinBosco Lai
    • G11C29/00G11C7/00
    • G11C29/56G11C5/04G11C11/401G11C29/1201G11C29/32G11C2029/5602
    • Described embodiments relate to a method of testing fully buffered memory modules that involves placing a buffer device, a test vectors generator, and a switch into a memory device tester, coupling the buffer device and the test vectors generator to the switch inside the tester, coupling the switch to an identical buffer device that is located on a memory module with plurality of DRAM devices, and testing the plurality of DRAM devices and the buffer device of the memory module. An apparatus implementing the method comprises a memory device tester, a memory bus, and a plurality of memory modules under test, the tester and the plurality of memory modules connected to the memory bus in a point-to-point manner, the tester comprising a buffer device, a test vectors generator, and a switch, the tester connected to the memory bus through the switch, each memory module under test having a plurality of DRAM devices and an identical buffer device.
    • 描述的实施例涉及一种测试完全缓冲的存储器模块的方法,该方法包括将缓冲器件,测试向量发生器和开关放置到存储器件测试器中,将缓冲器件和测试矢量发生器耦合到测试器内的开关,耦合 切换到位于具有多个DRAM设备的存储器模块上的相同缓冲器件,并测试存储器模块的多个DRAM器件和缓冲器件。 实现该方法的装置包括存储器件测试器,存储器总线和被测试的多个存储器模块,测试器和多个存储器模块以点到点的方式连接到存储器总线,测试器包括一个 缓冲设备,测试向量生成器和开关,测试器通过开关连接到存储器总线,每个被测试的存储器模块具有多个DRAM器件和相同的缓冲器器件。
    • 8. 发明授权
    • Method and apparatus for testing a fully buffered memory module
    • 用于测试完全缓冲存储器模块的方法和装置
    • US07539912B2
    • 2009-05-26
    • US11611390
    • 2006-12-15
    • Hong Liang ChanAllen LawrenceSunny ChangJoseph C. KleinBosco Lai
    • Hong Liang ChanAllen LawrenceSunny ChangJoseph C. KleinBosco Lai
    • G11C29/00
    • G11C29/56G11C5/04G11C11/401G11C29/1201G11C29/32G11C2029/5602
    • Described embodiments relate to a method of testing fully buffered memory modules that involves placing a buffer device, a test vectors generator, and a switch into a memory device tester, coupling the buffer device and the test vectors generator to the switch inside the tester, coupling the switch to an identical buffer device that is located on a memory module with plurality of DRAM devices, and testing the plurality of DRAM devices and the buffer device of the memory module. An apparatus implementing the method comprises a memory device tester, a memory bus, and a plurality of memory modules under test, the tester and the plurality of memory modules connected to the memory bus in a point-to-point manner, the tester comprising a buffer device, a test vectors generator, and a switch, the tester connected to the memory bus through the switch, each memory module under test having a plurality of DRAM devices and an identical buffer device.
    • 描述的实施例涉及一种测试完全缓冲的存储器模块的方法,该方法包括将缓冲器件,测试向量发生器和开关放置到存储器件测试器中,将缓冲器件和测试矢量发生器耦合到测试器内的开关,耦合 切换到位于具有多个DRAM设备的存储器模块上的相同缓冲器件,并测试存储器模块的多个DRAM器件和缓冲器件。 实现该方法的装置包括存储器件测试器,存储器总线和被测试的多个存储器模块,测试器和多个存储器模块以点到点的方式连接到存储器总线,测试器包括一个 缓冲设备,测试向量生成器和开关,测试器通过开关连接到存储器总线,每个被测试的存储器模块具有多个DRAM器件和相同的缓冲器器件。