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1. 发明授权

US5455924A Apparatus and method for partial execution blocking of instructions following a data cache miss 失效
标题翻译：在数据高速缓存未命中之后部分执行阻塞指令的装置和方法
公开(公告)号：US5455924A
公开(公告)日：1995-10-03
申请号：US15655
申请日：1993-02-09
申请人： Sunil R. Shenoy , James W. Wong
发明人： Sunil R. Shenoy , James W. Wong
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3836 , G06F12/0859
摘要： A partially blocking data cache having improved microprocessor performance while maintaining data consistency between external memory and cache memory. The data cache of the present invention is used in a computer system and is partially blocking in that this cache will block the execution of any store instructions subsequent to an outstanding load instruction that missed the cache. The present invention offers increased microprocessor efficiency by allowing execution of subsequent load instructions while less than a predetermined number of preceding load instructions are still outstanding. The present invention utilizes a counter within the data cache unit to track the number of outstanding load misses. The present invention provides increased performance without undue or overly complex modifications to existing caching systems. The present invention operates advantageously within a computer system having a relatively large number of registers associated with the microprocessor such that store instructions represent a relatively small number of the instructions executed by the microprocessor.
摘要翻译：具有改进的微处理器性能的部分阻塞数据高速缓存，同时保持外部存储器和高速缓冲存储器之间的数据一致性。本发明的数据高速缓存在计算机系统中被使用，并且部分阻塞，因为该高速缓冲存储器将在错过高速缓存的未完成的加载指令之后阻止任何存储指令的执行。本发明通过允许执行后续加载指令来提供增加的微处理器效率，同时小于预定数量的先前加载指令仍然未决。本发明利用数据高速缓存单元内的计数器来跟踪未完成的负载未命中的数量。本发明提供增加的性能，而不会对现有的缓存系统进行过度或过度复杂的修改。本发明有利地在具有与微处理器相关联的相对较多数量的寄存器的计算机系统内运行，使得存储指令表示由微处理器执行的相对较少数量的指令。

2. 发明授权

US5870599A Computer system employing streaming buffer for instruction preetching 失效
标题翻译：计算机系统采用流缓冲器进行指令预处理
公开(公告)号：US5870599A
公开(公告)日：1999-02-09
申请号：US953226
申请日：1997-10-17
申请人： Glenn J. Hinton , Ashwani K. Gupta , Sunil R. Shenoy
发明人： Glenn J. Hinton , Ashwani K. Gupta , Sunil R. Shenoy
IPC分类号： G06F9/38 , G06F12/08 , G06F9/00 , G06F12/00
CPC分类号： G06F9/3814 , G06F12/0859 , G06F9/3802 , G06F12/0862 , G06F2212/6022
摘要： Streaming buffer renaming for memory accesses issued by a microprocessor to an external memory via a system bus allows up to N fetch accesses at any one time for M physical streaming buffer locations, where N is greater than M. When a fetch within the processor misses the instruction cache, the fetch address is placed in the streaming buffer. When the data has been fetched from the external memory, it is returned to the streaming buffer and placed into one of the M physical buffer locations. The data within the streaming buffer is returned to the instruction cache of the processor only if it is to be used in accordance with the computer program being executed.
摘要翻译：用于通过系统总线由微处理器发送到外部存储器的存储器访问的流缓冲器重命名允许在任何一个时间对于N个大于M的物理流缓冲器位置进行N次获取访问。当处理器中的提取错过指令缓存，将获取地址放置在流缓冲区中。当从外部存储器中取出数据时，它返回到流缓冲器并放入M个物理缓冲区之一。流缓冲器中的数据只有在要根据正在执行的计算机程序使用时才返回到处理器的指令高速缓存。

3. 发明授权

US5493667A Apparatus and method for an instruction cache locking scheme 失效
标题翻译：一种指令缓存锁定方案的装置和方法
公开(公告)号：US5493667A
公开(公告)日：1996-02-20
申请号：US15541
申请日：1993-02-09
申请人： Scott B. Huck , Konrad K. Lai , Sunil R. Shenoy , Larry O. Smith
发明人： Scott B. Huck , Konrad K. Lai , Sunil R. Shenoy , Larry O. Smith
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/126 , G06F12/0864
摘要： An instruction locking apparatus and method for a cache memory allowing execution time predictability and high speed performance. The present invention implements a cache locking scheme in a two set associative instruction cache that utilizes a specially designed Least Recently Used (LRU) unit to effectively lock a first portion of the instruction cache to allow high speed and predictable execution time for time critical program code sections residing in the first portion while leaving another portion of the instruction cache free to operate as an instruction cache for other, non-critical, code sections. The present invention provides the above features in a system that is virtually transparent to the program code and does not require a variety of complex or specialized instructions or address coding methods. The present invention is flexible in that the two set associative instruction cache is transformed into what may be thought of as a static RAM in cache, and in addition, a direct map cache unit. Several different time critical code sections may be loaded and locked into the cache at different times.
摘要翻译：一种用于缓存的指令锁定装置和方法，其允许执行时间可预测性和高速性能。本发明在两组关联指令高速缓冲存储器中实现高速缓存锁定方案，其利用专门设计的最近使用（LRU）单元来有效地锁定指令高速缓存的第一部分，以允许用于时间关键程序代码的高速度和可预测的执行时间驻留在第一部分中的部分，同时使指令高速缓存的另一部分可自由地作为用于其他非关键代码段的指令高速缓存。本发明在系统中提供对程序代码实际上是透明的并且不需要各种复杂或专门的指令或地址编码方法的上述特征。本发明的灵活性在于，将两组关联指令高速缓存转换成可以被认为是高速缓存中的静态RAM的内容，另外还有直接映射缓存单元。可以在不同的时间将几个不同的时间关键代码段加载并锁定到高速缓存中。

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