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1. 发明授权

US07265382B2 Method and apparatus employing integrated metrology for improved dielectric etch efficiency 失效
标题翻译：采用集成计量学方法和设备，提高介电蚀刻效率
公开(公告)号：US07265382B2
公开(公告)日：2007-09-04
申请号：US10293595
申请日：2002-11-12
申请人： Dimitris Lymberopoulos , Gary Hsueh , Sukesh Mohan
发明人： Dimitris Lymberopoulos , Gary Hsueh , Sukesh Mohan
IPC分类号： H01L23/58 , H01L21/66 , G01N23/00
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for processing a semiconductor wafer is provided for reducing dimensional variation by feeding forward information relating to photoresist mask CD and profile and underlying layer thickness measured at several points on the wafer to adjust the next process the inspected wafer will undergo (e.g., the etch process). After the processing step, dimensions of a structure formed by the process, such as the CD and depth of a trench formed by the process, are measured at several points on the wafer, and this information is fed back to the process tool to adjust the process for the next wafer to further reduce dimensional variation. In certain embodiments, the CD, profile, thickness and depth measurements, etch processing and post-etch cleaning are performed at a single module in a controlled environment. All of the transfer and processing steps performed by the module are performed in a clean environment, thereby increasing yield by avoiding exposing the wafer to the atmosphere and possible contamination between steps.
摘要翻译：提供了一种用于处理半导体晶片的方法和装置，用于通过馈送与光致抗蚀剂掩模CD相关的前向信息以及在晶片上的几个点处测量的轮廓和下层厚度来减小尺寸变化，以调整被检查的晶片将经历的下一个处理（例如，蚀刻工艺）。在处理步骤之后，在晶片的几个点处测量由该工艺形成的结构的尺寸，例如CD和由该工艺形成的沟槽的深度，并将该信息反馈到处理工具以调整处理下一个晶片以进一步减小尺寸变化。在某些实施例中，在受控环境中的单个模块上执行CD，轮廓，厚度和深度测量，蚀刻处理和蚀刻后清洁。模块执行的所有转移和处理步骤都在干净的环境中进行，从而通过避免将晶片暴露在大气中并在步骤之间可能的污染来提高产量。

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