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1. 发明授权

US07469401B2 Method for using partitioned masks to build a chip 有权
标题翻译：使用分区掩码构建芯片的方法
公开(公告)号：US07469401B2
公开(公告)日：2008-12-23
申请号：US11359229
申请日：2006-02-22
申请人： Subhrajit Bhattacharya , John Darringer , Daniel L. Ostapko
发明人： Subhrajit Bhattacharya , John Darringer , Daniel L. Ostapko
IPC分类号： G06F17/50
CPC分类号： H01L27/0207
摘要： A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A method is provided comprising printing a set of component cores onto a die at predetermined locations with a reusable mask set; providing a custom blocking mask that includes opaque regions that positionally correspond with the component cores on the die; superimposing the custom blocking mask with a generic array type cell mask to form superimposed masks; and using the superimposed masks to print generic array type cells onto the die with the exception of the predetermined locations where the set of component cores reside.
摘要翻译：掩模复用方法过程，其中使用通用数组类型单元结构掩码和自定义阻止掩码来实现软逻辑。提供了一种方法，包括：在具有可重复使用的掩模组的预定位置处将一组部件芯片打印到管芯上; 提供自定义阻挡掩模，其包括与裸片上的部件芯位置对应的不透明区域; 将自定义阻止掩码与通用数组类型的单元格掩码叠加以形成叠加的掩码; 并且使用叠加的掩模将通用阵列类型的单元格打印到管芯上，除了组件核心所在的预定位置之外。

2. 发明授权

US07420388B2 Power gating techniques able to have data retention and variability immunity properties 有权
标题翻译：电源门控技术能够具有数据保留和可变性的抗扰性
公开(公告)号：US07420388B2
公开(公告)日：2008-09-02
申请号：US11498009
申请日：2006-08-01
申请人： Subhrajit Bhattacharya
发明人： Subhrajit Bhattacharya
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0008 , H03K19/0016
摘要： A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf-Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.
摘要翻译：电源门控半导体集成电路包括：（1）被电源门控的逻辑电路，所述逻辑电路具有虚拟接地轨; （2）设置在所述虚拟接地轨和地轨之间的脚踏装置，用于减少所述逻辑电路的功耗; 和（3）与所述脚踏装置并联设置的虚拟轨道电压钳，用于限制虚拟接地轨上的电压，虚拟轨电压钳包括至少一个NFET。总共NFET NFET连接到集成电路的虚拟接地轨，用作虚拟轨道电压钳和脚踏器件。扫描一定数量的N max-VC NFET，并执行电压钳位的功能，并且剩余的（N-N-N-N-MAX-VC） NFET执行电源门控。通过根据所制造的集成电路的测试来调整量N max-VC 来实现变异性抗扰度的制造变异性免疫和调谐。

3. 发明申请

US20070196958A1 Method for using partitioned masks to build a chip 有权
标题翻译：使用分区掩码构建芯片的方法
公开(公告)号：US20070196958A1
公开(公告)日：2007-08-23
申请号：US11359229
申请日：2006-02-22
申请人： Subhrajit Bhattacharya , John Darringer , Daniel Ostapko
发明人： Subhrajit Bhattacharya , John Darringer , Daniel Ostapko
IPC分类号： H01L21/82 , H01L21/331
CPC分类号： H01L27/0207
摘要： A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A method is provided comprising printing a set of component cores onto a die at predetermined locations with a reusable mask set; providing a custom blocking mask that includes opaque regions that positionally correspond with the component cores on the die; superimposing the custom blocking mask with a generic array type cell mask to form superimposed masks; and using the superimposed masks to print generic array type cells onto the die with the exception of the predetermined locations where the set of component cores reside.
摘要翻译：掩模复用方法过程，其中使用通用数组类型单元结构掩码和自定义阻止掩码来实现软逻辑。提供了一种方法，包括：在具有可重复使用的掩模组的预定位置处将一组部件芯片打印到管芯上; 提供自定义阻挡掩模，其包括与裸片上的部件芯位置对应的不透明区域; 将自定义阻止掩码与通用数组类型的单元格掩码叠加以形成叠加的掩码; 并且使用叠加的掩模将通用阵列类型的单元格打印到管芯上，除了组件核心所在的预定位置之外。

4. 发明申请

US20060091913A1 Power gating techniques able to have data retention and variability immunity properties 有权
标题翻译：电源门控技术能够具有数据保留和可变性的抗扰性
公开(公告)号：US20060091913A1
公开(公告)日：2006-05-04
申请号：US10978067
申请日：2004-10-28
申请人： Subhrajit Bhattacharya
发明人： Subhrajit Bhattacharya
IPC分类号： H03K19/096
CPC分类号： H03K19/0008 , H03K19/0016
摘要： A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf−Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.
摘要翻译：电源门控半导体集成电路包括：（1）被电源门控的逻辑电路，所述逻辑电路具有虚拟接地轨; （2）设置在所述虚拟接地轨和地轨之间的脚踏装置，用于减少所述逻辑电路的功耗; 和（3）与所述脚踏装置并联设置的虚拟轨道电压钳，用于限制虚拟接地轨上的电压，虚拟轨电压钳包括至少一个NFET。总共NFET NFET连接到集成电路的虚拟接地轨，用作虚拟轨道电压钳和脚踏器件。扫描一定数量的N max-VC NFET，并执行电压钳位的功能，并且剩余的（N-N-N-N-MAX-VC） NFET执行电源门控。通过根据所制造的集成电路的测试来调整量N max-VC 来实现变异性抗扰度的制造变异性免疫和调谐。

5. 发明授权

US07870531B2 System for using partitioned masks to build a chip 有权
标题翻译：使用分区掩码构建芯片的系统
公开(公告)号：US07870531B2
公开(公告)日：2011-01-11
申请号：US12117841
申请日：2008-05-09
申请人： Subhrajit Bhattacharya , John Darringer , Daniel L. Ostapko
发明人： Subhrajit Bhattacharya , John Darringer , Daniel L. Ostapko
IPC分类号： G06F17/50
CPC分类号： H01L27/0207
摘要： A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components; a generic array type cell mask; and a custom blocking mask that includes blocking regions that positionally correspond with a set of IP components printed on a die.
摘要翻译：掩模复用方法过程，其中使用通用数组类型单元结构掩码和自定义阻止掩码来实现软逻辑。提供一种系统，其包括具有对应于多个硬知识产权（IP）组件的多个可重复使用的掩模的掩模组; 通用数组类型的单元格掩码; 以及自定义阻挡掩模，其包括与印刷在管芯上的一组IP部件位置对应的阻挡区域。

6. 发明申请

US20080216037A1 SYSTEM FOR USING PARTITIONED MASKS TO BUILD A CHIP 有权
标题翻译：使用分割面罩制造芯片的系统
公开(公告)号：US20080216037A1
公开(公告)日：2008-09-04
申请号：US12117841
申请日：2008-05-09
申请人： Subhrajit Bhattacharya , John Darringer , Daniel L. Ostapko
发明人： Subhrajit Bhattacharya , John Darringer , Daniel L. Ostapko
IPC分类号： G06F17/50
CPC分类号： H01L27/0207
摘要： A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components; a generic array type cell mask; and a custom blocking mask that includes blocking regions that positionally correspond with a set of IP components printed on a die.
摘要翻译：掩模复用方法过程，其中使用通用数组类型单元结构掩码和自定义阻止掩码来实现软逻辑。提供一种系统，其包括具有对应于多个硬知识产权（IP）组件的多个可重复使用的掩模的掩模组; 通用数组类型的单元格掩码; 以及自定义阻挡掩模，其包括与印刷在管芯上的一组IP部件位置对应的阻挡区域。

7. 发明申请

US20060267629A1 Power gating techniques able to have data retention and variability immunity properties 有权
公开(公告)号：US20060267629A1
公开(公告)日：2006-11-30
申请号：US11498009
申请日：2006-08-01
申请人： Subhrajit Bhattacharya
发明人： Subhrajit Bhattacharya
IPC分类号： H03K19/003
CPC分类号： H03K19/0008 , H03K19/0016
摘要： A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf-Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.

8. 发明授权

US07126370B2 Power gating techniques able to have data retention and variability immunity properties 有权
公开(公告)号：US07126370B2
公开(公告)日：2006-10-24
申请号：US10978067
申请日：2004-10-28
申请人： Subhrajit Bhattacharya
发明人： Subhrajit Bhattacharya
IPC分类号： H03K19/003
CPC分类号： H03K19/0008 , H03K19/0016
摘要： A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf−Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.

9. 发明授权

US06993740B1 Methods and arrangements for automatically interconnecting cores in systems-on-chip 失效
标题翻译：芯片中芯片自动互连的方法和布置
公开(公告)号：US06993740B1
公开(公告)日：2006-01-31
申请号：US09542024
申请日：2000-04-03
申请人： Reinaldo A. Bergamaschi , Subhrajit Bhattacharya
发明人： Reinaldo A. Bergamaschi , Subhrajit Bhattacharya
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/66
摘要： A method and algorithms for creating correct-by-construction interconnections among complex intellectual property (IP) cores with hundreds of pins. The methods contemplated herein significantly reduce the time, complexity and potential for errors associated with systems-on-chip (SoC) integration.
摘要翻译：一种用于在具有数百个引脚的复杂知识产权（IP）内核之间创建正确构建互连的方法和算法。本文中考虑的方法显着地减少了与片上系统（SoC）集成相关的错误的时间，复杂性和潜力。

10. 发明授权

US5748647A Low cost testing method for register transfer level circuits 失效
标题翻译：寄存器传输级电路的低成本测试方法
公开(公告)号：US5748647A
公开(公告)日：1998-05-05
申请号：US741990
申请日：1996-10-31
申请人： Subhrajit Bhattacharya , Sujit Dey
发明人： Subhrajit Bhattacharya , Sujit Dey
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/3185 , G06F17/50
CPC分类号： G01R31/318586 , G01R31/318392
摘要： An alternative method for testing circuits (H-SCAN) which retains the main advantage of full scan testing, namely, the ability to use combinational automatic test pattern generation (ATPG), while eliminating the high area overhead the long test application time associated with full, scan test methods. The method provides a practical test methodology that can be easily applied to any RT-level specification. The method uses existing connections of registers and other structures available in a high-level specification of a circuit without necessitating the use of scan flip-flops. Test application time is reduced by using the parallelism inherent in the circuit design to load multiple flip-flops in a single clock cycle, without having to add parallel scan chains as done in traditional parallel scan approaches.
摘要翻译：一种用于测试电路（H-SCAN）的替代方法，其保留了全扫描测试的主要优点，即使用组合自动测试模式生成（ATPG）的能力，同时消除了与完全相关的长测试应用时间的高区域开销，扫描测试方法。该方法提供了可以轻松应用于任何RT级别规范的实用测试方法。该方法使用寄存器和电路的高级规范中可用的其他结构的现有连接，而不需要使用扫描触发器。通过使用电路设计中固有的并行性来减少测试应用时间，以在单个时钟周期内加载多个触发器，而不必像传统的并行扫描方法那样添加并行扫描链。

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