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1. 发明授权

US10340023B1 Method and system for determining bit values in non-volatile memory 有权
公开(公告)号：US10340023B1
公开(公告)日：2019-07-02
申请号：US15923247
申请日：2018-03-16
申请人： Storart Technology Co., Ltd.
发明人： Hsiang-En Peng , Sheng-Wei Yuan , Hou-Yun Lee
IPC分类号： G11C11/34 , G11C16/06 , G11C29/50 , G11C16/26 , G11C29/42
摘要： A method and a system for determining bit values in a non-volatile memory having a number of cells each for storing a bit value are disclosed. The method includes the steps of: a) providing a first test sensing voltage to the cells and calculating a cell count; b) providing another test sensing voltage to the cells and calculating a difference of the cell counts between this step and previous step; c) providing still another test sensing voltage and calculating another difference of the cell counts between this step and previous step; d) processing step c) for N times; e) calculating differential amounts of cell counts and assigning an index number to each group of cells; f) choosing a voltage as an updated sensing voltage.

2. 发明授权

US10270474B1 Partial concatenated coding system using algebraic code and LDPC code 有权
公开(公告)号：US10270474B1
公开(公告)日：2019-04-23
申请号：US15890432
申请日：2018-02-07
申请人： Storart Technology Co., Ltd.
发明人： Pei-Yu Shih , Tsung-Yu Wu
IPC分类号： H03M13/29 , H03M13/11
摘要： A partial concatenated coding system using an algebraic code and LDPC code is disclosed. The partial concatenated coding system includes an ECC encoder, a received codeword monitoring module and an ECC decoder. The ECC encoder has a LDPC code encoding module and an algebraic code encoding module. The ECC decoder has a LDPC code decoding module and an algebraic code decoding module. Comparing with conventional concatenating coding systems, the present invention has advantages of less spare spaces, better error-correcting performance, lower hardware complexity, better decoding throughput and fixable code length.

3. 发明申请

US20180018090A1 METHOD FOR TRANSFERRING COMMAND FROM HOST TO DEVICE CONTROLLER AND SYSTEM USING THE SAME 审中-公开
公开(公告)号：US20180018090A1
公开(公告)日：2018-01-18
申请号：US15212529
申请日：2016-07-18
申请人： Storart Technology Co.,Ltd.
发明人： Cheng Wei LU
IPC分类号： G06F3/06
摘要： A method for transferring a command from a host to a device controller and a system using the method are disclosed. The method includes the steps of: A. determining a segment size; B. dividing a command into a number of sections each having a size the same as the segment size; C. sequentially distributing the sections to n groups; D. changing distributing order to a reverse order or keeping the same distributing order in step C if a cycle of distribution is finished while there are sections left for distributing; E. restructuring the section(s) in each group as a sub-command after all sections are distributed; and F. providing the sub-commands to a device controller synchronously.

4. 发明授权

US09720821B2 Adaptive compression data storing method for non-volatile memories and system using the same 有权
公开(公告)号：US09720821B2
公开(公告)日：2017-08-01
申请号：US14488877
申请日：2014-09-17
申请人： Storart Technology Co., Ltd.
发明人： Jui Hui Hung , Ming-Yi Chu
IPC分类号： G06F12/02 , H03M7/30
CPC分类号： G06F12/0246 , G06F2212/401 , H03M7/3086
摘要： An adaptive compression data storing method for non-volatile memories and a system using the method are disclosed. The system includes a host interface unit, a data compressor, a padding unit, a buffer, a combining unit, and a mapping table unit. By combining some compressed data in one page, the present invention can settle the problem that space for storing a compressed data that can not be utilized. Further, lifetime of non-volatile memories can be extended.

5. 发明授权

US09641194B2 Method for encoding multi-mode of BCH codes and encoder thereof 有权
公开(公告)号：US09641194B2
公开(公告)日：2017-05-02
申请号：US14288904
申请日：2014-05-28
申请人： Storart Technology Co., Ltd.
发明人： Jui Hui Hung , Chih Nan Yen
IPC分类号： H03M13/00 , H03M13/15
CPC分类号： H03M13/152 , H03M13/611 , H03M13/616 , H03M13/6516
摘要： A method for encoding multi-modes of BCH codes and an associated encoder is disclosed. The method has the steps of: building a number of encoding matrices; combining the encoding matrices with one side aligned to form a combined matrix; seeking common sub-expressions (CSEs) in the combined matrix, and encoding a message using the combined matrix.

6. 发明申请

US20170070239A1 DECODING ALGORITHM WITH ENHANCED PARITY CHECK MATRIX AND RE-ENCODING SCHEME FOR LDPC CODE 有权
标题翻译：用加密奇偶校验矩阵解码算法和LDPC编码的重新编码方案
公开(公告)号：US20170070239A1
公开(公告)日：2017-03-09
申请号：US14847214
申请日：2015-09-08
申请人： Storart Technology Co.,Ltd.
发明人： Jui Hui HUNG
IPC分类号： H03M13/11 , H03M13/00
CPC分类号： H03M13/1108 , H03M13/116 , H03M13/1185 , H03M13/3776 , H03M13/6502 , H03M13/6544
摘要： A decoding algorithm with an enhanced parity check matrix and a re-encoding scheme for LDPC codes is disclosed. The decoding algorithm includes the steps of: providing the enhanced parity check matrix; receiving a message part of an original codeword encoded by a generator matrix from the enhanced parity check matrix; setting a LLR for each bit node of the enhanced parity check matrix; processing hard decision on the message part of the original codeword; encoding the message part of the original codeword by the generator matrix to generate a new codeword having a generated parity part; comparing the original parity part with the generated parity part to find out bits of difference; voting candidate error bits to choose the most probably erratic bits; modifying LLR of the chosen bits to have a modified codeword; and processing a conventional iterative decoding procedure on the modified codeword to have a processed codeword.
摘要翻译：公开了一种具有增强的奇偶校验矩阵和用于LDPC码的重新编码方案的解码算法。解码算法包括以下步骤：提供增强的奇偶校验矩阵; 从增强型奇偶校验矩阵接收由发生器矩阵编码的原始码字的消息部分; 为增强型奇偶校验矩阵的每个比特节点设置一个LLR; 对原始码字的消息部分进行硬判决; 通过发生器矩阵对原始码字的消息部分进行编码，以产生具有生成的奇偶校验部分的新码字; 将原始奇偶校验部分与生成的奇偶校验部分进行比较，以找出差异位; 投票候选错误位选择最可能不稳定的位; 修改所选位的LLR以具有修改的码字; 以及对经修改的码字处理传统的迭代解码过程以具有经处理的码字。

7. 发明授权

US09417848B2 Serial multiply accumulator for galois field 有权
标题翻译：用于伽罗瓦域的串行乘法累加器
公开(公告)号：US09417848B2
公开(公告)日：2016-08-16
申请号：US14228763
申请日：2014-03-28
申请人： Storart Technology Co., Ltd.
发明人： Jui Hui Hung , Chih Nan Yen
IPC分类号： G06F7/72 , G06F7/544
CPC分类号： G06F7/724 , G06F7/5443
摘要： A serial multiply accumulator (MAC) for operation of two multiplications and one addition over Galois field is disclosed. The MAC includes a first element feeding circuit, a second element feeding circuit, a number of first calculating circuits and a second calculating circuit. By re-arranging the circuit design, many elements used in the conventional MAC, such as XOR gates and registers, can be saved. The present invention has an advantage of lower area cost.
摘要翻译：公开了用于在Galois域上进行两次乘法和一次加法的串行乘法累加器（MAC）。 MAC包括第一元件供给电路，第二元件馈送电路，多个第一计算电路和第二计算电路。通过重新布置电路设计，可以节省常规MAC中使用的许多元件，如XOR门和寄存器。本发明具有面积成本较低的优点。

8. 发明授权

US09337869B2 Encoding and syndrome computing co-design circuit for BCH code and method for deciding the same 有权
标题翻译：用于BCH码的编码和综合计算协同设计电路及其决定方法
公开(公告)号：US09337869B2
公开(公告)日：2016-05-10
申请号：US14265929
申请日：2014-04-30
申请人： Storart Technology Co., Ltd.
发明人： Jui Hui Hung , Chih Nan Yen
IPC分类号： H03M13/00 , H03M13/15
CPC分类号： H03M13/152 , H03M13/157 , H03M13/1595 , H03M13/616
摘要： An encoding and syndrome computing co-design circuit for BCH code and a method for deciding the circuit are disclosed. The method includes the steps of: building up matrices of XR, XG and XS according to p parallel computations and 2t syndromes; building up FP; building up F′; building up F″; building up matrix of [XSRG F″]; and designing a circuit which fulfills the operation of [XSRG F″].
摘要翻译：公开了用于BCH码的编码和综合计算协同设计电路以及用于确定电路的方法。该方法包括以下步骤：根据p并行计算和2t综合征建立XR，XG和XS的矩阵; 建立FP; 建立F' 建立F“; 建立[XSRG F“]矩阵; 并设计满足[XSRG F“]操作的电路。

9. 发明授权

US10283209B2 Method for detecting problem cells of SATA SSD and SATA SSD having self-detecting function looking for problem cells 有权
公开(公告)号：US10283209B2
公开(公告)日：2019-05-07
申请号：US14847197
申请日：2015-09-08
申请人： Storart Technology Co., Ltd.
发明人： Chun Hsien Lin
IPC分类号： G11C29/44 , G11C29/04 , G11C16/34 , G11C29/50
摘要： A method for detecting problem cells of a SATA SSD and a SATA SSD having self-detecting function looking for problem cells are disclosed. The method includes the steps of: providing a detecting program used to detect aged and died cells in a SATA SSD; writing the detecting program to a MCU (Micro Control Unit) in the SATA SSD; pulling high electric potential of a communicating pin of a SATA connector of the SATA SSD to initiate the detecting program; collecting location data of aged and died cells in the SATA SSD by the detecting program; and storing the location data in a storage area in the SSD. The present invention utilizes the DAS/DSS pin as a channel to initiate detecting program. It has advantages of using current interface of SSD, no effort on taking apart hardware and automatically running the detecting program without human control.

10. 发明授权

US09973212B2 Decoding algorithm with enhanced parity check matrix and re-encoding scheme for LDPC code 有权
公开(公告)号：US09973212B2
公开(公告)日：2018-05-15
申请号：US14847214
申请日：2015-09-08
申请人： Storart Technology Co., Ltd.
发明人： Jui Hui Hung
IPC分类号： H03M13/00 , H03M13/11 , H03M13/37
CPC分类号： H03M13/1108 , H03M13/116 , H03M13/1185 , H03M13/3776 , H03M13/6502 , H03M13/6544
摘要： A decoding algorithm with an enhanced parity check matrix and a re-encoding scheme for LDPC codes is disclosed. The decoding algorithm includes the steps of: providing the enhanced parity check matrix; receiving a message part of an original codeword encoded by a generator matrix from the enhanced parity check matrix; setting a LLR for each bit node of the enhanced parity check matrix; processing hard decision on the message part of the original codeword; encoding the message part of the original codeword by the generator matrix to generate a new codeword having a generated parity part; comparing the original parity part with the generated parity part to find out bits of difference; voting candidate error bits to choose the most probably erratic bits; modifying LLR of the chosen bits to have a modified codeword; and processing a conventional iterative decoding procedure on the modified codeword to have a processed codeword.

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