专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09367107B2 Method and system for controlling reset state change in a system-on-a-chip device 有权
标题翻译：用于控制片上系统设备中的复位状态变化的方法和系统
公开(公告)号：US09367107B2
公开(公告)日：2016-06-14
申请号：US13276596
申请日：2011-10-19
申请人： Steven William Maddigan
发明人： Steven William Maddigan
IPC分类号： G06F1/24 , G06F1/32 , G06F9/44
CPC分类号： G06F1/24 , G06F1/3206 , G06F9/4401
摘要： A method and system are set forth for enabling software control of a power management unit (PMU) in a System-On-a-Chip (SoC) device to effect changes in power state without having to adjust external board level states. In one embodiment, once the SoC system controller has been booted, it communicates with the PMU over a communication bus and is able to request changes in power states without requiring external trigger events. Complete remote control of power states according to the method and system set forth herein provides flexibility when debugging and testing SoC devices because there is no need to alter external board states. Also, providing programmable changes in reset states as an alternative to full system reset preserves state data so that the system can be restarted efficiently and quickly from known conditions.
摘要翻译：提出了一种方法和系统，用于使得能够在片上系统（SoC）设备中的功率管理单元（PMU）的软件控制来实现功率状态的改变而不必调整外部板级状态。在一个实施例中，一旦SoC系统控制器被启动，它通过通信总线与PMU进行通信，并且能够请求在电源状态的改变而不需要外部触发事件。根据本文提出的方法和系统，完全对电源状态的远程控制提供了调试和测试SoC设备时的灵活性，因为不需要改变外部电路板状态。此外，提供复位状态的可编程更改作为全系统复位的替代方案，保留状态数据，以便可以从已知条件有效和快速地重新启动系统。

2. 发明授权

US08898502B2 Clock domain crossing interface 有权
标题翻译：时钟域交叉界面
公开(公告)号：US08898502B2
公开(公告)日：2014-11-25
申请号：US13176160
申请日：2011-07-05
申请人： Steven William Maddigan , Dimitri Gabriel Epassa Habib
发明人： Steven William Maddigan , Dimitri Gabriel Epassa Habib
IPC分类号： G06F1/12 , H04L7/02 , G06F5/10
CPC分类号： G06F1/12 , G06F5/10 , G06F2205/102 , H04L7/005 , H04L7/02
摘要： A flexible and scalable bi-directional CDC interface is set forth between clock domains in a SoC device. The interface comprises a pulse sync circuit for receiving a pulse synchronized to the source clock domain and in response outputting a busy signal to the source clock domain and outputting the pulse synchronized to said destination clock domain; an input register for latching data from said source clock domain in response to a transition of said source clock in the event said busy signal is not active and preventing said data from being latched in the event said busy signal is active so as not to corrupt previously latched data; and an output register for receiving said pulse from said pulse sync circuit and in response latching said pulse from said input register on a transition of said destination clock.
摘要翻译：在SoC设备的时钟域之间提供灵活且可扩展的双向CDC接口。接口包括脉冲同步电路，用于接收与源时钟域同步的脉冲，并且响应于将忙信号输出到源时钟域并输出与所述目的地时钟域同步的脉冲; 输入寄存器，用于在所述忙信号不活动的情况下响应于所述源时钟的转变来锁存来自所述源时钟域的数据，并且在所述忙信号有效的情况下防止所述数据被锁存，以便先前不会损坏锁定数据; 以及输出寄存器，用于从所述脉冲同步电路接收所述脉冲，并且响应于在所述目的地时钟的转变时从所述输入寄存器锁存所述脉冲。

3. 发明申请

US20130103935A1 METHOD AND SYSTEM FOR PROGRAMMABLE POWER STATE CHANGE IN A SYSTEM-ON-A-CHIP DEVICE 有权
标题翻译：系统中的片上设备可编程电源状态变化的方法和系统
公开(公告)号：US20130103935A1
公开(公告)日：2013-04-25
申请号：US13276596
申请日：2011-10-19
申请人： Steven William MADDIGAN
发明人： Steven William MADDIGAN
IPC分类号： G06F9/24 , G06F1/00
CPC分类号： G06F1/24 , G06F1/3206 , G06F9/4401
摘要： A method and system are set forth for enabling software control of a power management unit (PMU) in a System-On-a-Chip (SoC) device to effect changes in power state without having to adjust external board level states. In one embodiment, once the SoC system controller has been booted, it communicates with the PMU over a communication bus and is able to request changes in power states without requiring external trigger events. Complete remote control of power states according to the method and system set forth herein provides flexibility when debugging and testing SoC devices because there is no need to alter external board states. Also, providing programmable changes in reset states as an alternative to full system reset preserves state data so that the system can be restarted efficiently and quickly from known conditions.
摘要翻译：提出了一种方法和系统，用于使得能够在片上系统（SoC）设备中的功率管理单元（PMU）的软件控制来实现功率状态的改变而不必调整外部板级状态。在一个实施例中，一旦SoC系统控制器被启动，它通过通信总线与PMU进行通信，并且能够请求在电源状态的改变而不需要外部触发事件。根据本文提出的方法和系统，完全对电源状态的远程控制提供了调试和测试SoC设备时的灵活性，因为不需要改变外部电路板状态。此外，提供复位状态的可编程更改作为全系统复位的替代方案，保留状态数据，以便可以从已知条件有效和快速地重新启动系统。

4. 发明申请

US20130013950A1 CLOCK DOMAIN CROSSING INTERFACE 有权
标题翻译：时钟交叉界面
公开(公告)号：US20130013950A1
公开(公告)日：2013-01-10
申请号：US13176160
申请日：2011-07-05
申请人： Steven William Maddigan , Dimitri Gabriel Epassa Habib
发明人： Steven William Maddigan , Dimitri Gabriel Epassa Habib
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F5/10 , G06F2205/102 , H04L7/005 , H04L7/02
摘要： A flexible and scalable bi-directional CDC interface is set forth between clock domains in a SoC device. The interface comprises a pulse sync circuit for receiving a pulse synchronized to the source clock domain and in response outputting a busy signal to the source clock domain and outputting the pulse synchronized to said destination clock domain; an input register for latching data from said source clock domain in response to a transition of said source clock in the event said busy signal is not active and preventing said data from being latched in the event said busy signal is active so as not to corrupt previously latched data; and an output register for receiving said pulse from said pulse sync circuit and in response latching said pulse from said input register on a transition of said destination clock.
摘要翻译：在SoC设备的时钟域之间提供灵活且可扩展的双向CDC接口。接口包括脉冲同步电路，用于接收与源时钟域同步的脉冲，并且响应于将忙信号输出到源时钟域并输出与所述目的地时钟域同步的脉冲; 输入寄存器，用于在所述忙信号不活动的情况下响应于所述源时钟的转变来锁存来自所述源时钟域的数据，并且在所述忙信号有效的情况下防止所述数据被锁存，以便先前不会损坏锁定数据; 以及输出寄存器，用于从所述脉冲同步电路接收所述脉冲，并且响应于在所述目的地时钟的转变时从所述输入寄存器锁存所述脉冲。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式