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1. 发明申请

US20100320532A1 TRENCH GATE MOSFET AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： TRENCH GATE MOSFET及其制造方法
公开(公告)号：US20100320532A1
公开(公告)日：2010-12-23
申请号：US12739341
申请日：2008-10-22
申请人： Steven Thomas Peake , Philip Rutter , Christopher Martin Rogers , Miron Drobnis , Andrew Butler
发明人： Steven Thomas Peake , Philip Rutter , Christopher Martin Rogers , Miron Drobnis , Andrew Butler
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/2251 , H01L21/26586 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/66734
摘要： A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.
摘要翻译：沟槽栅极MOS场效应晶体管，其具有从紧邻沟槽侧壁的相同导电类型的沟道容纳区域（3）延伸的窄的轻掺杂区域。窄区域可以自对准到沟槽中的下多晶硅屏蔽区域的顶部，或者可以延伸沟槽的整个深度。窄区域有利地放宽制造公差，否则需要上部多晶硅沟槽栅极与体 - 漏接合部紧密对准。

2. 发明授权

US08357971B2 Trench gate MOSFET and method of manufacturing the same 有权
标题翻译：沟槽栅MOSFET及其制造方法
公开(公告)号：US08357971B2
公开(公告)日：2013-01-22
申请号：US12739341
申请日：2008-10-22
申请人： Steven Thomas Peake , Philip Rutter , Christopher Martin Rogers , Miron Drobnis , Andrew Butler
发明人： Steven Thomas Peake , Philip Rutter , Christopher Martin Rogers , Miron Drobnis , Andrew Butler
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/2251 , H01L21/26586 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/66734
摘要： A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.
摘要翻译：沟槽栅极MOS场效应晶体管，其具有从紧邻沟槽侧壁的相同导电类型的沟道容纳区域（3）延伸的窄的轻掺杂区域。窄区域可以与沟槽中的下多晶硅屏蔽区域的顶部自对准，或者可以延伸沟槽的整个深度。窄区域有利地放宽制造公差，否则需要上部多晶硅沟槽栅极与体 - 漏接合部紧密对准。

3. 发明申请

US20120037980A1 EDGE TERMINATION REGION 有权
标题翻译：边缘终止区域
公开(公告)号：US20120037980A1
公开(公告)日：2012-02-16
申请号：US13210308
申请日：2011-08-15
申请人： Steven Thomas Peake , Philip Rutter
发明人： Steven Thomas Peake , Philip Rutter
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4238 , H01L29/7811
摘要： An isolation region (14) is formed between an edge termination region (2) having deep trenches (20,34) and the central region (4). The isolation region includes gate fingers (18) extending from the edge gate trench regions (28) to the gate trenches (6) in the central region (4) to electrically connect the edge gate trench regions to the gate trenches (6) in the central region. The isolation region also includes isolation fingers (22,24) extending from the edge termination region (2) towards the central region (4) and gate between the gate fingers (18) for reducing the breakdown voltage with a RESURF effect.
摘要翻译：在具有深沟槽（20,34）的边缘终端区域（2）和中心区域（4）之间形成隔离区域（14）。隔离区域包括从边缘栅极沟槽区域（28）延伸到中心区域（4）中的栅极沟槽（6）的栅极指（18），以将栅极沟槽区域电连接到栅极沟槽（6）中央区域。隔离区域还包括从边缘终端区域（2）向中心区域（4）延伸的隔离指状物（22,24）以及栅极指状物（18）之间的栅极，用于以RESURF效应降低击穿电压。

4. 发明授权

US06979865B2 Cellular mosfet devices and their manufacture 失效
标题翻译：蜂窝式mosfet设备及其制造
公开(公告)号：US06979865B2
公开(公告)日：2005-12-27
申请号：US10503171
申请日：2003-01-23
申请人： Steven Thomas Peake , Christopher Martin Rogers
发明人： Steven Thomas Peake , Christopher Martin Rogers
IPC分类号： H01L21/336 , H01L27/07 , H01L29/06 , H01L29/78 , H01L29/872 , H01L21/8234
CPC分类号： H01L29/7813 , H01L27/0727 , H01L29/0619 , H01L29/0653 , H01L29/0696 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： A cellular MOSFET device has a cellular area (CA) comprising active MOSFET cells, and one or more Schottky diode areas (SA) accommodated within a deep end region (15) at a lateral boundary of this cellular area (CA). This deep end region (150) is laterally divided so as to accommodate the diode area (SA) therein. A diode portion (14d) of the first conductivity type of the drain region (14) extends upwardly through the laterally-divided deep end region (150) that is of the second conductivity type. The Schotty barrier (100) formed with this diode portion (14d) terminates laterally in the laterally-divided portions (150deep end region (150) which serve as a guard region and field-relief region for the Schottky diode.
摘要翻译：蜂窝MOSFET器件具有包含有源MOSFET单元的蜂窝区域（CA）和容纳在该蜂窝区域（CA）的侧边界处的深端区域（15）内的一个或多个肖特基二极管区域（SA）。该深端区域（150）被横向划分以便容纳其中的二极管区域（SA）。第一导电类型的漏极区域（14）的二极管部分（14d）向上延伸穿过第二导电类型的横向分割的深端区域（150）。形成有该二极管部分（14d）的Schotty势垒（100）在用作肖特基二极管的保护区域和场平面区域的横向分割部分（150深端区域（150））中横向终止。

5. 发明授权

US08901638B2 Trench-gate semiconductor device 有权
标题翻译：沟槽栅半导体器件
公开(公告)号：US08901638B2
公开(公告)日：2014-12-02
申请号：US13055742
申请日：2009-07-27
申请人： Steven Thomas Peake , Phil Rutter
发明人： Steven Thomas Peake , Phil Rutter
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/7397
摘要： A trench-gate semiconductor device is disclosed, in which the player (10,6) which forms the body region (in a n-channel device) extends adjacent the trench (4) deeper into the device, to lie adjacent a lower trench electrode (3b, 3c). Since the p-layer extension (6) forms part of the channel, it must be very low doped, in order not to increase unduly the channel resistance in the on-state. The replacement of some of the out-diffusion resistance in the drift region by the (smaller) channel resistance results in a lower over-all Rdson. In the off-state, the p-layer forms, together with the underlying n-drift layer, a non-abrupt function, so that the depletion region in the off-state extends closer to the top surface (2) than for a conventional RSO trench-MOS, being split between the p- and n-layers, rather than all being in the n-drift region. The invention does not require a RESURF device structure, so has wide process windows, since the dopant levels and layer thicknesses do not have to be controlled to provide charge balancing.
摘要翻译：公开了一种沟槽栅半导体器件，其中形成身体区域（在n沟道器件中）的游戏者（10,6）在沟槽（4）附近延伸到设备中更深处以邻近下沟槽电极（3b，3c）。由于p层延伸部（6）形成沟道的一部分，所以必须是非常低的掺杂，以便不导致导通状态下的沟道电阻过度增加。通过（较小的）通道电阻来替代漂移区域中的一些外扩散电阻导致较低的全部Rdson。在关闭状态下，p层与下面的n漂移层一起形成非突然的功能，使得截止状态下的耗尽区域比常规的更靠近顶表面（2）延伸。 RSO沟槽MOS，分为p层和n层之间，而不是全部在n漂移区域中。本发明不需要RESURF器件结构，因此具有宽的工艺窗口，因为不必控制掺杂剂水平和层厚度以提供电荷平衡。

6. 发明授权

US08513733B2 Edge termination region of a semiconductor device 有权
标题翻译：半导体器件的边缘端接区域
公开(公告)号：US08513733B2
公开(公告)日：2013-08-20
申请号：US13210308
申请日：2011-08-15
申请人： Steven Thomas Peake , Philip Rutter
发明人： Steven Thomas Peake , Philip Rutter
IPC分类号： H01L27/108 , H01L29/66 , H01L21/336 , H01L21/331
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4238 , H01L29/7811
摘要： An isolation region (14) is formed between an edge termination region (2) having deep trenches (20,34) and the central region (4). The isolation region includes gate fingers (18) extending from the edge gate trench regions (28) to the gate trenches (6) in the central region (4) to electrically connect the edge gate trench regions to the gate trenches (6) in the central region. The isolation region also includes isolation fingers (22,24) extending from the edge termination region (2) towards the central region (4) and gate between the gate fingers (18) for reducing the breakdown voltage with a RESURF effect.
摘要翻译：在具有深沟槽（20,34）的边缘终端区域（2）和中心区域（4）之间形成隔离区域（14）。隔离区域包括从边缘栅极沟槽区域（28）延伸到中心区域（4）中的栅极沟槽（6）的栅极指（18），以将栅极沟槽区域电连接到栅极沟槽（6）中央区域。隔离区域还包括从边缘终端区域（2）向中心区域（4）延伸的隔离指状物（22,24）以及栅极指状物（18）之间的栅极，用于以RESURF效应降低击穿电压。

7. 发明申请

US20110121384A1 TRENCH-GATE SEMICONDUCTOR DEVICE 有权
标题翻译： TRENCH-GATE半导体器件
公开(公告)号：US20110121384A1
公开(公告)日：2011-05-26
申请号：US13055742
申请日：2009-07-27
申请人： Steven Thomas Peake , Phil Rutter
发明人： Steven Thomas Peake , Phil Rutter
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/7397
摘要： A trench-gate semiconductor device is disclosed, in which the p-layer (10,6) which forms the body region (in a n-channel device) extends adjacent the trench (4) deeper into the device, to lie adjacent a lower trench electrode (3b, 3c). Since the p-layer extension (6) forms part of the channel, it must be very low doped, in order not to increase unduly the channel resistance in the on-state. The re-placement of some of the out-diffusion resistance in the drift region by the (smaller) channel resistance results in a lower over-all Rdson. In the off-state, the p-layer forms, together with the underlying n-drift layer, a non-abrupt function, so that the depletion region in the off-state extends closer to the top surface (2) than for a conventional RSO trench-MOS, being split between the p- and n-layers, rather than all being in the n-drift region. The invention does not require a RESURF device structure, so has wide process windows, since the dopant levels and layer thicknesses do not have to be controlled to provide charge balancing.
摘要翻译：公开了一种沟槽栅半导体器件，其中形成体区（在n沟道器件中）的p层（10,6）在沟槽（4）附近延伸到器件中更靠近下部沟槽电极（3b，3c）。由于p层延伸部（6）形成沟道的一部分，所以必须是非常低的掺杂，以便不导致导通状态下的沟道电阻过度增加。通过（较小）沟道电阻重新放置漂移区域中的一些外扩散电阻导致较低的全部Rdson。在关闭状态下，p层与下面的n漂移层一起形成非突然的功能，使得截止状态下的耗尽区域比常规的更靠近顶表面（2）延伸。 RSO沟槽MOS，分为p层和n层之间，而不是全部在n漂移区域中。本发明不需要RESURF器件结构，因此具有宽的工艺窗口，因为不必控制掺杂剂水平和层厚度以提供电荷平衡。

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