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1. 发明授权

US08871596B2 Method of multiple patterning to form semiconductor devices 有权
标题翻译：多重图形化形成半导体器件的方法
公开(公告)号：US08871596B2
公开(公告)日：2014-10-28
申请号：US13555240
申请日：2012-07-23
申请人： Kuang-Jung Chen , Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Sen Liu
发明人： Kuang-Jung Chen , Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Sen Liu
IPC分类号： H01L21/31
CPC分类号： H01L21/0274 , H01L21/26586 , H01L21/3081 , H01L21/76229 , H01L21/76283 , H01L29/517 , H01L29/66575 , H01L29/78
摘要： A method of forming different structures of a semiconductor device using a single mask and a hybrid photoresist. The method includes: applying a first photoresist layer on a semiconductor substrate; patterning the first photoresist layer using a photomask to form a first patterned photoresist layer; using the first patterned photoresist layer to form a first structure of a semiconductor device; removing the first patterned photoresist layer; applying a second photoresist layer on the semiconductor substrate; patterning the second photoresist layer using the photomask to form a second patterned photoresist layer; using the second patterned photoresist layer to form a second structure of a semiconductor device; removing the second patterned photoresist layer; and wherein either the first or the second photoresist layer is a hybrid photoresist layer comprising a hybrid photoresist.
摘要翻译：使用单个掩模和混合光致抗蚀剂形成半导体器件的不同结构的方法。该方法包括：在半导体衬底上施加第一光致抗蚀剂层; 使用光掩模图案化第一光致抗蚀剂层以形成第一图案化光致抗蚀剂层; 使用所述第一图案化的光致抗蚀剂层形成半导体器件的第一结构; 去除第一图案化光致抗蚀剂层; 在所述半导体衬底上施加第二光致抗蚀剂层; 使用光掩模图案化第二光致抗蚀剂层以形成第二图案化光致抗蚀剂层; 使用所述第二图案化的光致抗蚀剂层形成半导体器件的第二结构; 去除第二图案化光致抗蚀剂层; 并且其中所述第一或第二光致抗蚀剂层是包含混合光致抗蚀剂的混合光致抗蚀剂层。

2. 发明授权

US08835305B2 Method of fabricating a profile control in interconnect structures 有权
标题翻译：在互连结构中制作轮廓控制的方法
公开(公告)号：US08835305B2
公开(公告)日：2014-09-16
申请号：US13562953
申请日：2012-07-31
申请人： Chih-Chao Yang , Shyng-Tsong Chen , Samuel S. Choi , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Wai-Kin Li , Christopher J. Penny , Shom Ponoth , Yunpeng Yin
发明人： Chih-Chao Yang , Shyng-Tsong Chen , Samuel S. Choi , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Wai-Kin Li , Christopher J. Penny , Shom Ponoth , Yunpeng Yin
IPC分类号： H01L21/4763 , H01L23/12 , H01L21/768 , H01L23/522
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/76813 , H01L21/76831 , H01L21/76844 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.
摘要翻译：可以通过在形成介电材料之前形成电介质材料的每个通孔开口内形成轮廓控制衬垫来控制通孔的轮廓，然后在电介质材料内形成线路开口。在形成线路开口期间在每个通孔开口内存在轮廓控制衬垫防止存在于线路开口下方并且邻近通孔开口的电介质材料部分的拐角的四舍五入。

3. 发明授权

US08715907B2 Developable bottom antireflective coating compositions for negative resists 有权
标题翻译：用于负性抗蚀剂的可开发的底部抗反射涂料组合物
公开(公告)号：US08715907B2
公开(公告)日：2014-05-06
申请号：US13206796
申请日：2011-08-10
申请人： Kuang-Jung Chen , Steven J. Holmes , Wu-Song Huang , Sen Liu
发明人： Kuang-Jung Chen , Steven J. Holmes , Wu-Song Huang , Sen Liu
IPC分类号： G03F7/09 , G03F7/11 , G03F7/30
CPC分类号： G03F7/0382 , C09J133/14 , G03F7/091 , G03F7/094 , G03F7/095
摘要： A negative developable bottom antireflective coating (NDBARC) material includes a polymer containing an aliphatic alcohol moiety, an aromatic moiety, and a carboxylic acid moiety. The NDBARC composition is insoluble in a typical resist solvent such as propylene glycol methyl ether acetate (PGMEA) after coating and baking. The NDBARC material also includes a photoacid generator, and optionally a crosslinking compound. In the NDBARC material, the carboxylic acid provides the developer solubility, while the alcohol alone, the carboxylic acid alone, or their combination provides the PGMEA resistance. The NDBARC material has resistance to the resist solvent, and thus, intermixing does not occur between NDBARC and resist during resist coating over NDBARC. After exposure and bake, the lithographically exposed portions of both the negative photoresist and the NDBARC layer become insoluble in developer due to the chemically amplified crosslinking of the polymers in negative resist and NDBARC layer in the lithographically exposed portions.
摘要翻译：负显影底部抗反射涂层（NDBARC）材料包括含有脂族醇部分，芳族部分和羧酸部分的聚合物。 NDBARC组合物在涂布和烘烤后不溶于典型的抗蚀剂溶剂如丙二醇甲基醚乙酸酯（PGMEA）。 NDBARC材料还包括光致酸发生剂和任选的交联化合物。在NDBARC材料中，羧酸提供了显影剂的溶解度，而单独的醇，单独的羧酸或它们的组合提供了PGMEA的抗性。 NDBARC材料对抗蚀剂溶剂具有抗性，因此在NDBARC的抗蚀涂层期间，NDBARC和抗蚀剂之间不会发生混合。在曝光和烘烤之后，由于在光刻曝光部分中的负光刻胶和NDBARC层中的聚合物的化学扩展交联，负光致抗蚀剂和NDBARC层的光刻曝光部分变得不溶于显影剂。

4. 发明申请

US20140004712A1 DEVELOPABLE BOTTOM ANTIREFLECTIVE COATING COMPOSITION AND PATTERN FORMING METHOD USING THEREOF 有权
标题翻译：可开发的底部抗反射涂料组合物及其使用的图案形成方法
公开(公告)号：US20140004712A1
公开(公告)日：2014-01-02
申请号：US13537177
申请日：2012-06-29
申请人： Kuang-Jung Chen , Steven J. Holmes , Wu-Song Huang , Ranee Kwong , Sen Liu
发明人： Kuang-Jung Chen , Steven J. Holmes , Wu-Song Huang , Ranee Kwong , Sen Liu
IPC分类号： G03F7/20 , H01L21/265 , C09K3/00
CPC分类号： G03F7/11 , C08F220/26 , C08L33/066 , C08L33/16 , C08L2312/00 , C09D133/066 , G03F7/0046 , G03F7/038 , G03F7/0392 , G03F7/0397 , G03F7/091 , G03F7/30 , G03F7/322 , G03F7/40 , H01L21/0274 , H01L21/0276 , H01L21/265 , C08L2205/025
摘要： The present invention relates to a developable bottom antireflective coating (BARC) composition and a pattern forming method using the BARC composition. The BARC composition includes a first polymer having a first carboxylic acid moiety, a hydroxy-containing alicyclic moiety, and a first chromophore moiety; a second polymer having a second carboxylic acid moiety, a hydroxy-containing acyclic moiety, and a second chromophore moiety; a crosslinking agent; and a radiation sensitive acid generator. The first and second chromophore moieties each absorb light at a wavelength from 100 nm to 400 nm. In the patterning forming method, a photoresist layer is formed over a BARC layer of the BARC composition. After exposure, unexposed regions of the photoresist layer and the BARC layer are selectively removed by a developer to form a patterned structure in the photoresist layer. The BARC composition and the pattern forming method are especially useful for implanting levels.
摘要翻译：本发明涉及一种可显影底部抗反射涂层（BARC）组合物和使用该BARC组合物的图案形成方法。 BARC组合物包括具有第一羧酸部分，含羟基脂环族部分和第一发色团部分的第一聚合物; 具有第二羧酸部分的第二聚合物，含羟基的无环部分和第二发色团部分; 交联剂; 和辐射敏感酸发生器。第一和第二发色团部分各自吸收波长从100nm到400nm的光。在图案形成方法中，在BARC组合物的BARC层上形成光致抗蚀剂层。曝光后，通过显影剂选择性地除去光致抗蚀剂层和BARC层的未曝光区域，以在光致抗蚀剂层中形成图案化结构。 BARC组合物和图案形成方法对于植入水平特别有用。

5. 发明授权

US08568604B2 CMOS gate structures fabricated by selective oxidation 有权
标题翻译：通过选择性氧化制造的CMOS栅极结构
公开(公告)号：US08568604B2
公开(公告)日：2013-10-29
申请号：US12186075
申请日：2008-08-05
申请人： Bruce B. Doris , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Bruce B. Doris , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： B44C1/22 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/823828 , H01L21/823864
摘要： A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial material that is deposited over a structure layer and covered by a cover layer. The sacrificial material layer and the cover layer are patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the material layer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.
摘要翻译：用于形成亚光刻结构的侧壁图像转印工艺采用沉积在结构层上并被覆盖层覆盖的牺牲材料层。牺牲材料层和覆盖层用常规抗蚀剂图案化并蚀刻以形成牺牲芯棒。心轴的边缘在低温下在等离子体中被氧化或氮化，之后剥离材料层和覆盖层，留下亚光刻的侧壁。侧壁用作硬掩模来蚀刻栅极导体层中的亚光刻栅极结构。

6. 发明申请

US20130216776A1 DUAL HARD MASK LITHOGRAPHY PROCESS 有权
标题翻译：双硬掩模平版印刷工艺
公开(公告)号：US20130216776A1
公开(公告)日：2013-08-22
申请号：US13402068
申请日：2012-02-22
申请人： John C. Arnold , Sean D. Burns , Steven J. Holmes , David V. Horak , Muthumanickam Sankarapandian , Yunpeng Yin
发明人： John C. Arnold , Sean D. Burns , Steven J. Holmes , David V. Horak , Muthumanickam Sankarapandian , Yunpeng Yin
IPC分类号： B32B3/00 , G03F7/20
CPC分类号： H01L23/5226 , G03F7/0035 , G03F7/091 , G03F7/094 , H01L21/0332 , H01L21/0338 , H01L21/3081 , H01L21/3088 , H01L21/31144 , H01L21/76811 , H01L21/76816 , H01L2924/0002 , Y10T428/24355 , H01L2924/00
摘要： A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.
摘要翻译：在互连级介质层上的第一金属硬掩模层用线图案图案化。在第一金属硬掩模层上方施加至少一个介电材料层，第二金属硬掩模层，第一有机平坦化层（OPL）和第一光致抗蚀剂。第一通孔图案从第一光致抗蚀剂层转移到第二金属硬掩模层中。第二OPL和第二光致抗蚀剂被施加和图案化，第二通孔图案被转移到第二金属硬掩模层中。第一和第二通孔图案的第一复合图案被转移到至少一个介电材料层中。将第一复合图案与第一金属硬掩模层中的开口的面积限制的第二复合图案被转移到互连级介质层中。

7. 发明申请

US20120168931A1 CARBON NANOTUBE STRUCTURES FOR ENHANCEMENT OF THERMAL DISSIPATION FROM SEMICONDUCTOR MODULES 有权
标题翻译：用于增强半导体模块散热的碳纳米管结构
公开(公告)号：US20120168931A1
公开(公告)日：2012-07-05
申请号：US13418454
申请日：2012-03-13
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , Charles W. Koburger, III , Krishna V. Singh
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , Charles W. Koburger, III , Krishna V. Singh
IPC分类号： H01L23/36 , H01L21/50 , B82Y99/00 , B82Y40/00
CPC分类号： H01L23/373 , B82Y10/00 , B82Y40/00 , H01L21/6835 , H01L23/3157 , H01L23/433 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/81 , H01L24/94 , H01L29/0657 , H01L2221/6835 , H01L2221/68377 , H01L2224/0401 , H01L2224/05026 , H01L2224/05186 , H01L2224/05561 , H01L2224/05564 , H01L2224/05571 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/10135 , H01L2224/113 , H01L2224/11845 , H01L2224/13021 , H01L2224/13076 , H01L2224/131 , H01L2224/13147 , H01L2224/13184 , H01L2224/13187 , H01L2224/13193 , H01L2224/16221 , H01L2224/1703 , H01L2224/17515 , H01L2224/274 , H01L2224/73253 , H01L2224/81139 , H01L2224/81191 , H01L2224/81193 , H01L2224/81493 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/14 , H01L2924/04953 , H01L2224/05552
摘要： Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.
摘要翻译：公开了在后表面上具有碳纳米管（CNT）的保护簇的改进的半导体晶片结构的实施方案和形成改进的半导体晶片结构的方法。还公开了在后表面上具有暴露的CNT的半导体模块的实施例，用于与散热器一起提供增强的散热以及使用所公开的半导体晶片结构形成半导体模块的方法。

8. 发明授权

US07994060B2 Dual exposure track only pitch split process 有权
标题翻译：双曝光轨道只有音高分割过程
公开(公告)号：US07994060B2
公开(公告)日：2011-08-09
申请号：US12551801
申请日：2009-09-01
申请人： Sean D. Burns , Matthew E. Colburn , Steven J. Holmes
发明人： Sean D. Burns , Matthew E. Colburn , Steven J. Holmes
IPC分类号： H01L21/311 , H01L21/469
CPC分类号： H01L21/31144 , G03F7/0035 , H01L21/0271 , H01L21/0338
摘要： An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat.
摘要翻译：集成电路形成为具有比这种结构的横向尺寸更紧密地在一起的结构，例如用于通过暗场分割俯仰技术以最小可光滑分辨尺寸形成的电子元件的接触。对于需要蚀刻多个顺序施加的和图案化的抗蚀剂层中的每一个的硬标记的分割间距处理的可接受的覆盖精度和处理效率和处理量通过使用酸敏感的硬标记材料和通过抗蚀剂中的图案化孔接触硬掩模的区域的酸性外涂层。通过烘烤酸性外涂层来激活硬掩模的接触区域以进行显影。

9. 发明授权

US07892968B2 Via gouging methods and related semiconductor structure 有权
标题翻译：通过沟槽方法和相关的半导体结构
公开(公告)号：US07892968B2
公开(公告)日：2011-02-22
申请号：US12017141
申请日：2008-01-21
申请人： Shyng-Tsong Chen , Steven J. Holmes , David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： Shyng-Tsong Chen , Steven J. Holmes , David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/31144 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing the protective coating over horizontal surfaces of the dielectric material. A semiconductor structure may include a via having an interface with a conductor, the interface including a three-dimensionally shaped region extending into and past a surface of the conductor, wherein an outer edge of the three-dimensionally shaped region is distanced from an outermost surface of the via.
摘要翻译：公开了通孔沟槽的方法和相关的半导体结构。在一个实施例中，该方法包括在电介质材料中形成通孔，通孔与导体对准; 在介电材料和通孔开口上形成保护涂层; 通过刨花进行; 并且在电介质材料的水平表面上去除保护涂层。半导体结构可以包括与导体具有界面的通孔，所述界面包括延伸到导体表面中并经过导体表面的三维成形区域，其中三维成形区域的外边缘与最外表面的通道。

10. 发明授权

US07834384B2 Simultaneous conditioning of a plurality of memory cells through series resistors 有权
标题翻译：通过串联电阻同时调节多个存储单元
公开(公告)号：US07834384B2
公开(公告)日：2010-11-16
申请号：US12060922
申请日：2008-04-02
申请人： Toshijaru Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Chung H. Lam , Gerhard I. Meijer
发明人： Toshijaru Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Chung H. Lam , Gerhard I. Meijer
IPC分类号： H01L27/00
CPC分类号： H01L27/0629 , H01L27/101 , H01L27/24
摘要： Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.
摘要翻译：公开了一种半导体结构和方法，其允许在具有多个存储器单元的非易失性存储器件中同时对多个存储器元件进行电压/电流调节。该结构和方法结合使用与存储器元件串联连接的电阻器来限制电流通过存储器元件。具体地，该方法和结构在存储器单元上方的晶片表面上和/或存储器单元内的永久串联电阻器上并入一个橡皮布暂时串联电阻器。在调节过程中，一旦调节了这些电阻，这些电阻就可以保护各个存储元件中的过渡金属氧化物免受损坏（即烧坏）。

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