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1. 发明授权

US07892957B2 Gate CD trimming beyond photolithography 有权
标题翻译：门光盘修剪超出光刻
公开(公告)号：US07892957B2
公开(公告)日：2011-02-22
申请号：US12212784
申请日：2008-09-18
申请人： Steven Arthur Vitale
发明人： Steven Arthur Vitale
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28123
摘要： A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a conductive material, such as polysilicon, is formed over the gate dielectric layer. The gate layer is patterned to form a gate electrode having a first horizontal dimension. One or more growth-stripping operations are performed to reduce a critical dimension of the gate electrode to a second horizontal dimension, where the second horizontal dimension is less than the first horizontal dimension.
摘要翻译：以选定的临界尺寸制造半导体器件。栅电介质层形成在半导体本体上。在栅极电介质层上形成由诸如多晶硅的导电材料构成的栅极层。图案化栅极层以形成具有第一水平尺寸的栅电极。执行一个或多个生长剥离操作以将栅电极的临界尺寸减小到第二水平尺寸，其中第二水平尺寸小于第一水平尺寸。

2. 发明申请

US20090017607A1 GATE CD TRIMMING BEYOND PHOTOLITHOGRAPHY 有权
公开(公告)号：US20090017607A1
公开(公告)日：2009-01-15
申请号：US12212784
申请日：2008-09-18
申请人： STEVEN ARTHUR VITALE
发明人： STEVEN ARTHUR VITALE
IPC分类号： H01L21/28
CPC分类号： H01L21/28123
摘要： A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a conductive material, such as polysilicon, is formed over the gate dielectric layer. The gate layer is patterned to form a gate electrode having a first horizontal dimension. One or more growth-stripping operations are performed to reduce a critical dimension of the gate electrode to a second horizontal dimension, where the second horizontal dimension is less than the first horizontal dimension.
摘要翻译：以选定的临界尺寸制造半导体器件。栅电介质层形成在半导体本体上。在栅极电介质层上形成由诸如多晶硅的导电材料构成的栅极层。图案化栅极层以形成具有第一水平尺寸的栅电极。执行一个或多个生长剥离操作以将栅电极的临界尺寸减小到第二水平尺寸，其中第二水平尺寸小于第一水平尺寸。

3. 发明授权

US07687396B2 Method of forming silicided gates using buried metal layers 有权
标题翻译：使用掩埋金属层形成硅化物栅的方法
公开(公告)号：US07687396B2
公开(公告)日：2010-03-30
申请号：US11617897
申请日：2006-12-29
申请人： Steven Arthur Vitale , Shaofeng Yu
发明人： Steven Arthur Vitale , Shaofeng Yu
IPC分类号： H01L21/44
CPC分类号： H01L21/28097
摘要： A method comprises forming a gate stack comprising a polysilicon layer, a metal layer and a polysilicon layer over a gate dielectric and substrate. The metal layer is buried inside the gate stack to alloy the silicon and metal at the bottom of the gate. The gate stack is then etched to form a gate. A silicidation is then performed to form a silicide at the bottom of the gate. Optionally, a second metal layer may be formed on top of the gate stack. As such, during silicidation, a silicide may be formed at the top of the gate.
摘要翻译：一种方法包括在栅极电介质和衬底上形成包括多晶硅层，金属层和多晶硅层的栅极堆叠。金属层被埋在栅极堆叠内，以在栅极的底部合金硅和金属。然后蚀刻栅极堆叠以形成栅极。然后进行硅化，以在栅极的底部形成硅化物。可选地，第二金属层可以形成在栅叠层的顶部。因此，在硅化期间，可以在栅极的顶部形成硅化物。

4. 发明申请

US20080157258A1 METHOD OF FORMING SILICIDED GATES USING BURIED METAL LAYERS 有权
标题翻译：使用金属层形成硅胶门的方法
公开(公告)号：US20080157258A1
公开(公告)日：2008-07-03
申请号：US11617897
申请日：2006-12-29
申请人： Steven Arthur Vitale , Shaofeng Yu
发明人： Steven Arthur Vitale , Shaofeng Yu
IPC分类号： H01L29/66 , H01L21/283
CPC分类号： H01L21/28097
摘要： A method comprises forming a gate stack comprising a polysilicon layer, a metal layer and a polysilicon layer over a gate dielectric and substrate. The metal layer is buried inside the gate stack to alloy the silicon and metal at the bottom of the gate. The gate stack is then etched to form a gate. A silicidation is then performed to form a silicide at the bottom of the gate. Optionally, a second metal layer may be formed on top of the gate stack. As such, during silicidation, a silicide may be formed at the top of the gate.
摘要翻译：一种方法包括在栅极电介质和衬底上形成包括多晶硅层，金属层和多晶硅层的栅极堆叠。金属层被埋在栅极堆叠内，以在栅极的底部合金硅和金属。然后蚀刻栅极堆叠以形成栅极。然后进行硅化，以在栅极的底部形成硅化物。可选地，第二金属层可以形成在栅叠层的顶部。因此，在硅化期间，可以在栅极的顶部形成硅化物。

5. 发明授权

US07910289B2 Use of dual mask processing of different composition such as inorganic/organic to enable a single poly etch using a two-print-two-etch approach 有权
标题翻译：使用不同成分的双掩模加工，如无机/有机，可使用双印双蚀刻方法进行单层聚蚀刻
公开(公告)号：US07910289B2
公开(公告)日：2011-03-22
申请号：US11326392
申请日：2006-01-06
申请人： Benjamen Michael Rathsack , James Walter Blatchford , Steven Arthur Vitale
发明人： Benjamen Michael Rathsack , James Walter Blatchford , Steven Arthur Vitale
IPC分类号： G03F7/20
CPC分类号： H01L21/027 , H01L21/033 , H01L21/32139
摘要： In accordance with the invention, there are methods of making an integrated circuit, an integrated circuit device, and a computer readable medium. A method can comprise forming a first layer over a semiconductor substrate, forming a first mask layer over the semiconductor substrate, and using the first mask layer to pattern first features. The method can also include forming a second mask layer over the first features, using the second mask layer to pattern portions of the first features, removing the second mask layer, and removing the first mask layer.
摘要翻译：根据本发明，存在制造集成电路，集成电路器件和计算机可读介质的方法。一种方法可以包括在半导体衬底上形成第一层，在半导体衬底上形成第一掩模层，以及使用第一掩模层来图案化第一特征。该方法还可以包括在第一特征上形成第二掩模层，使用第二掩模层来图案化第一特征的部分，去除第二掩模层，以及去除第一掩模层。

6. 发明授权

US07494882B2 Manufacturing a semiconductive device using a controlled atomic layer removal process 有权
标题翻译：使用受控原子层去除工艺制造半导体器件
公开(公告)号：US07494882B2
公开(公告)日：2009-02-24
申请号：US11373662
申请日：2006-03-10
申请人： Steven Arthur Vitale
发明人： Steven Arthur Vitale
IPC分类号： H01L21/336
CPC分类号： H01L21/32139 , H01L21/0338 , H01L21/28035 , H01L21/32135 , H01L21/32137 , H01L29/78
摘要： A method for manufacturing a semiconductive device comprising forming a mask for a semiconductive device structure over a layer of a semiconductor substrate and partially etching the layer to form lateral and vertical surfaces. Thicknesses of one to several atomic diameters of atoms that comprise said layer are removed from the lateral surfaces and the vertical surfaces that are located under the mask to form a target dimension of a semiconductive device structure.
摘要翻译：一种用于制造半导体器件的方法，包括在半导体衬底的层上形成用于半导体器件结构的掩模，并部分蚀刻所述层以形成横向和垂直表面。从位于掩模下方的侧表面和垂直表面去除包含所述层的一至几个原子直径的原子的厚度，以形成半导体器件结构的目标尺寸。

7. 发明授权

US07439106B2 Gate CD trimming beyond photolithography 有权
标题翻译：门光盘修剪超出光刻
公开(公告)号：US07439106B2
公开(公告)日：2008-10-21
申请号：US11359670
申请日：2006-02-22
申请人： Steven Arthur Vitale
发明人： Steven Arthur Vitale
IPC分类号： H01L21/339
CPC分类号： H01L21/28123
摘要： A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a conductive material, such as polysilicon, is formed over the gate dielectric layer. The gate layer is patterned to form a gate electrode having a first horizontal dimension. One or more growth-stripping operations are performed to reduce a critical dimension of the gate electrode to a second horizontal dimension, where the second horizontal dimension is less than the first horizontal dimension.
摘要翻译：以选定的临界尺寸制造半导体器件。栅电介质层形成在半导体本体上。在栅极电介质层上形成由诸如多晶硅的导电材料构成的栅极层。图案化栅极层以形成具有第一水平尺寸的栅电极。执行一个或多个生长剥离操作以将栅电极的临界尺寸减小到第二水平尺寸，其中第二水平尺寸小于第一水平尺寸。

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