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1. 发明授权

US08094677B2 Multi-bus structure for optimizing system performance of a serial buffer 有权
标题翻译：多总线结构，用于优化串行缓冲器的系统性能
公开(公告)号：US08094677B2
公开(公告)日：2012-01-10
申请号：US11679824
申请日：2007-02-27
申请人： Steve Juan , Chi-Lie Wang , Ming-Shiung Chen
发明人： Steve Juan , Chi-Lie Wang , Ming-Shiung Chen
IPC分类号： H04J3/16
CPC分类号： H04L12/4015 , H04L47/10 , H04L47/2441
摘要： A serial buffer having a parser and multiple parallel processing paths is provided. The parser receives incoming packets, determines the type of each packet, and then routes each packet to a processing path that corresponds with the determined packet type. Packet types may include blocking priority packets (which implement bus slave operations), non-blocking priority packets (which access on-chip resources of the serial buffer) and data packets (which implement bus master operations). Because the different packet types are processed on parallel processing paths, the processing of one packet type does not interfere with the processing of other packet types. As a result, blocking conditions within the serial buffer are minimized.
摘要翻译：提供具有解析器和多个并行处理路径的串行缓冲器。解析器接收传入的分组，确定每个分组的类型，然后将每个分组路由到与确定的分组类型相对应的处理路径。分组类型可以包括阻塞优先分组（其实现总线从操作），非阻塞优先分组（其访问串行缓冲器的片上资源）和数据分组（其实现总线主机操作）。由于不同的分组类型在并行处理路径上被处理，所以一种分组类型的处理不会干扰其他分组类型的处理。结果，串行缓冲器内的阻塞条件最小化。

2. 发明申请

US20080205438A1 Multi-Bus Structure For Optimizing System Performance Of a Serial Buffer 有权
标题翻译：用于优化串行缓冲器的系统性能的多总线结构
公开(公告)号：US20080205438A1
公开(公告)日：2008-08-28
申请号：US11679824
申请日：2007-02-27
申请人： Steve Juan , Chi-Lie Wang , Ming-Shiung Chen
发明人： Steve Juan , Chi-Lie Wang , Ming-Shiung Chen
IPC分类号： H04J3/22
CPC分类号： H04L12/4015 , H04L47/10 , H04L47/2441
摘要： A serial buffer having a parser and multiple parallel processing paths is provided. The parser receives incoming packets, determines the type of each packet, and then routes each packet to a processing path that corresponds with the determined packet type. Packet types may include blocking priority packets (which implement bus slave operations), non-blocking priority packets (which access on-chip resources of the serial buffer) and data packets (which implement bus master operations). Because the different packet types are processed on parallel processing paths, the processing of one packet type does not interfere with the processing of other packet types. As a result, blocking conditions within the serial buffer are minimized.
摘要翻译：提供具有解析器和多个并行处理路径的串行缓冲器。解析器接收传入的分组，确定每个分组的类型，然后将每个分组路由到与确定的分组类型相对应的处理路径。分组类型可以包括阻塞优先分组（其实现总线从操作），非阻塞优先分组（其访问串行缓冲器的片上资源）和数据分组（其实现总线主机操作）。由于不同的分组类型在并行处理路径上被处理，所以一种分组类型的处理不会干扰其他分组类型的处理。结果，串行缓冲器内的阻塞条件最小化。

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